7.8. Parity detection

The L1 memory system instruction and data caches support parity detection on data arrays. There is one parity bit for each data byte. For data cache, because the dirty bit is also held in the data array, there is a corresponding parity bit to cover the dirty bit. Parity errors reported by instruction cache accesses result in precise prefetch aborts. Parity errors reported by data cache accesses result in imprecise data aborts.

Parity errors reported by instruction cache accesses are reported on a fetch-granularity basis, that is, if any byte within a fetch region contains a parity error, the parity error is reported on the first instruction in the fetch, although this instruction might not contain the parity error.

The Auxiliary Control Register bit [3], L1PE, controls parity errors reported by the L1 caches. Parity errors are enabled if the L1PE bit is set to 1.

If a cache access result is a parity error in the L1 data cache, then the L1 data cache and the L2 cache are unpredictable. No recovery is possible. The abort handler must:

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I