13.4.3. Floating-point exception Register, FPEXC

The FPEXC Register is accessible in privileged modes only.

The EN bit, FPEXC[30], is the NEON and VFP enable bit. Clearing EN disables the NEON and VFP coprocessor. The EN bit is cleared to 0 on reset.

Figure 13.5 shows the bit arrangement of the FPEXC Register.

Figure 13.5. Floating-Point Exception Register format


Table 13.10 shows how the bit values correspond with the FPEXC Register functions.

Table 13.10. Floating-Point Exception Register bit functions

Bits

Field

Function

[31]

-Reserved.

[30]

ENNEON and VFP enable bit. Setting the EN bit to 1 enables the NEON and VFP coprocessor. Reset clears EN to 0.
[29:0]-Reserved.

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