12.4.5. CP14 c1, Debug Status and Control Register

The DSCR is a read-only register that contains status and control information about the debug unit. Figure 12.5 shows the bit arrangement of the DSCR.

Note

For the APB interface, the DSCR is a read/write register.

Figure 12.5. Debug Status and Control Register format


Table 12.14 shows how the bit values correspond with the Debug Status and Control Register functions.

Table 12.14. Debug Status and Control Register bit functions

BitsFieldFunction

[31]

-

Reserved. RAZ, SBZP.

[30]

DTRRXfull

The DTRRXfull flag:

0 = DTRRX empty, reset value

1 = DTRRX full.

When set to 1, this flag indicates that there is data available in the Receive Data Transfer Register, DTRRX. It is automatically set to 1 on writes to the DTRRX by the debugger, and is cleared to 0 when the processor reads the CP14 DTR. If the flag is not set to 1, the DTRRX returns an Unpredictable value.

[29]

DTRTXfull

The DTRTXfull flag:

0 = DTRTX empty, reset value

1 = DTRTX full.

When set to 0, this flag indicates that the Transmit Data Transfer Register, DTRTX, is ready for data write. It is automatically set to 0 on reads of the DTRTX by the debugger, and is set to 1 when the processor writes to the CP14 DTR. If this bit is set to 1 and the core attempts to write to the DTRTX, the register contents are overwritten and the DTRTXfull flag remains set.

[28]

-

Reserved. RAZ, SBZP.

[27]

DTRRXfull_l

The latched DTRRXfull flag. This flag is read in one of the following ways:

  • using CP14 instruction

  • using the DSCR memory address

  • using the OSSRR memory address.

CP14 instruction returns an Unpredictable value for this bit.

DSCR memory address returns the same value as DTRRXfull.

OSSRR memory address returns the latched DTRRXfull value, that is, the value of DTRRXfull that the processor captured on the last DSCR memory address read.

If a write to the DTRRX APB address succeeds, DTRRXfull_l is set to 1.

[26]

DTRTXfull_l

The latched DTRTXfull flag. This flag is read in one of the following ways:

  • using CP14 instruction

  • using the DSCR memory address

  • using the OSSRR memory address.

CP14 instruction returns an Unpredictable value for this bit.

DSCR memory address returns the same value as DTRTXfull.

OSSRR memory address returns the latched DTRTXfull value, that is, the value of DTRTXfull that the processor captured on the last DSCR memory address read.

If a read to the DTRTX APB address succeeds, DTRTXfull_l is cleared to 0.

[25]

Sticky pipeline advance

Sticky pipeline advance bit. This bit enables the debugger to detect whether the processor is idle. In some situations, this might mean that the system bus port is deadlock. This bit is set to 1 every time the processor pipeline retires one instruction. A write to DRCR[3] clears this bit to 0. See Debug Run Control Register.

0 = no instruction has completed execution since the last time this bit was cleared, reset value

1 = an instruction has completed execution since the last time this bit was cleared.

[24]

InstrCompl_l

The latched InstrCompl flag. This flag is read in one of the following ways:

  • using CP14 instruction

  • using the DSCR memory address

  • using the OSSRR memory address.

CP14 instruction returns an Unpredictable value for this bit.

DSCR memory address returns the same value as InstrCompl.

OSSRR memory address returns the latched InstrCompl value, that is, the value of InstrCompl that the processor captured on the last DSCR memory address read.

If a write to the ITR APB address succeeds while in Stall or Nonblocking mode, InstrCompl_l and InstrCompl are cleared to 0.

If a write to the DTRRX APB address or a read to the DTRTX APB address succeeds while in Fast mode, InstrCompl_l and InstrCompl are cleared to 0.

InstrCompl is the instruction complete bit. This internal flag determines whether the processor has completed execution of an instruction issued through the APB interface.

0 = the processor is currently executing an instruction fetched from the ITR Register, reset value

1 = the processor is not currently executing an instruction fetched from the ITR Register.

[23:22]

-

Reserved. UNP, SBZP.

[21:20]

DTR access mode

DTR access mode. This is a read/write field. You can use this field to optimize DTR traffic between a debugger and the processor:

b00 = Nonblocking mode, reset value

b01 = Stall mode

b10 = Fast mode

b11 = reserved.

Note

  • This field only affects the behavior of DSCR, DTR, and ITR accesses through the APB interface, and not through CP14 debug instructions.

  • Nonblocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming jammed.

See DTR access mode for more information.

[19]

Discard imprecise abort

Discard imprecise abort. This read-only bit is set to 1 while the processor is in debug state and is cleared to 0 on exit from debug state. While this bit is set to 1, the processor does not record imprecise Data Aborts. However, the sticky imprecise Data Abort bit is set to 1.

0 = imprecise Data Aborts not discarded, reset value

1 = imprecise Data Aborts discarded.

[18][1]

Nonsecure state status

Nonsecure state status bit:

0 = the processor is in Secure state or the processor is in Monitor mode

1 = the processor is in Nonsecure state and is not in Monitor mode.

[17]a

Secure privileged noninvasive debug disabled

Secure privileged noninvasive debug disabled:

0 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is HIGH

1 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is LOW.

This value is the inverse of bit [6] of the Authentication Status Register. See Authentication Status Register.

[16]a

Secure privileged invasive debug disabled

Secure privileged invasive debug disabled:

0 = (DBGEN && SPIDEN) is HIGH

1 = (DBGEN && SPIDEN) is LOW.

This value is the inverse of bit [4] of the Authentication Status Register. See Authentication Status Register.

[15]

Monitor debug-mode

The Monitor debug-mode enable bit. This is a read/write bit.

0 = Monitor debug-mode disabled, reset value

1 = Monitor debug-mode enabled.

If Halting debug-mode is enabled, bit [14] is set to 1, then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGEN is LOW, DSCR[15] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value.

[14]Halting debug-mode

The Halting debug-mode enable bit. This is a read/write bit.

0 = Halting debug-mode disabled, reset value

1 = Halting debug-mode enabled.

If the external interface input DBGEN is LOW, DSCR[14] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value.

[13]

Execute instruction enable

Execute ARM instruction enable bit. This is a read/write bit.

0 = disabled, reset value

1 = enabled.

If this bit is set to 1 and an ITR write succeeds, the processor fetches an instruction from the ITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable.

[12]

CP14 user access disable

CP14 debug user access disable control bit. This is a read/write bit.

0 = CP14 debug user access enable, reset value

1 = CP14 debug user access disable.

If this bit is set to 1 and a User mode process tries to access any CP14 debug registers, the Undefined Instruction exception is taken.

[11]

Interrupt disable

Interrupts disable bit. This is a read/write bit.

0 = interrupts enabled, reset value

1 = interrupts disabled.

If this bit is set to 1, the IRQ and FIQ input signals are disabled. The external debugger can set this bit to 1 before it executes code in normal state as part of the debugging process. If this bit is set to 1, an interrupt does not take control of the program flow. For example, the debugger might use this bit to execute an OS service routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the routine execution.

[10]

DbgAck

Debug Acknowledge bit. This is a read/write bit. If this bit is set to 1, both the DBGACK and DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The external debugger can use this bit if it wants the system to behave as if the processor is in debug state. Some systems rely on DBGACK to determine whether the application or debugger generates the data accesses. The reset value is 0.

[9]

-

Reserved. UNP, SBZ.

[8]

Sticky Undefined

Sticky Undefined bit:

0 = No Undefined Instruction exception occurred in debug state since the last time this bit was cleared. This is the reset value.

1 = An Undefined Instruction exception has occurred while in debug state since the last time this bit was cleared.

This flag detects Undefined instruction exceptions generated by instructions issued to the processor through the ITR. This bit is set to 1 when an Undefined Instruction exception occurs while the processor is in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See Debug Run Control Register.

[7]Sticky imprecise abort

Sticky imprecise Data Abort bit:

0 = no imprecise Data Aborts occurred since the last time this bit was cleared, reset value

1 = an imprecise Data Abort occurred since the last time this bit was cleared.

This flag detects imprecise Data Aborts triggered by instructions issued to the processor through the ITR. This bit is set to 1 when an imprecise Data Abort occurs while the processor is in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See Debug Run Control Register.

[6]

Sticky precise abort

Sticky precise Data Abort bit:

0 = no precise Data Abort occurred since the last time this bit was cleared, reset value

1 = a precise Data Abort occurred since the last time this bit was cleared.

This flag detects precise Data Aborts generated by instructions issued to the processor through the ITR. This bit is set to 1 when a precise Data Abort occurs while the processor is in debug state. Writing a 1 to DRCR[2] clears this bit to 0. See Debug Run Control Register.

[5:2]

Entry

Method of entry bits. This is a read/write field.

b0000 = a DRCR[0] halting debug event occurred, reset value

b0001 = a breakpoint occurred

b0100 = an EDBGRQ halting debug event occurred

b0011 = a BKPT instruction occurred

b0101 = a vector catch occurred

b1000 = an OS unlock catch occurred

b1010 = a precise watchpoint occurred

other = reserved.

These bits are set to indicate any of:

  • the cause of a debug exception

  • the cause for entering debug state.

A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event.

[1]a

Core restarted

Core restarted bit:

0 = The processor is exiting debug state.

1 = The processor has exited debug state. This is the reset value.

The debugger can poll this bit to determine when the processor responds to a request to leave debug state.

[0]a

Core halted

Core halted bit:

0 = The processor is in normal state. This is the reset value.

1 = The processor is in debug state.

The debugger can poll this bit to determine when the processor has entered debug state.

[1] These bits always reflect the status of the processor and, therefore they return to their reset values if the particular reset event affects the processor. For example, a PRESETn event leaves these bits unchanged whereas a core reset event such as nPORESET or ARESETn sets DSCR[18] to a 0 and DSCR[1:0] to b10.


To access the Debug Status and Control Register, read CP14 c1 with:

MRC p14, 0, <Rd>, c0, c1, 0 ; Read Debug Status and Control Register

DTR access mode

You can use the DTR access mode field to optimize data transfer between a debugger and the processor.

The DTR access mode can be one of the following:

  • Nonblocking, this is the default mode

  • Stall

  • Fast.

In Nonblocking mode, the APB reads from the DTRTX and writes to the DTRRX and ITR are ignored if the appropriate READY flag is not set. In particular:

  • writes to DTRRX are ignored if DTRRXfull_l is set to 1

  • writes to ITR are ignored if InstrCompl_l is not set to 1

  • reads from DTRTX are ignored and return an Unpredictable value if DTRTXfull_l is not set to 1.

The debugger accessing these registers must first read the DSCR, and perform any of the following:

  • write to the DTRRX if the DTRRXfull_l flag was cleared to 0

  • write to the ITR if the InstrCompl_l flag was set to 1

  • read from the DTRTX if the DTRTXfull_l flag was set to 1.

Failure to read the DSCR before one of these operations leads to Unpredictable behavior.

In Stall mode, the APB accesses to DTRRX, DTRTX, and ITR stall under the following conditions:

  • writes to DTRRX are stalled until DTRRXfull is cleared to 0

  • writes to ITR are stalled until InstrCompl is set to 1

  • reads from DTRTX are stalled until DTRTXfull is set to 1.

Fast mode is similar to Stall mode except that in Fast mode, the processor fetches an instruction from the ITR when a DTRRX write or DTRTX read succeeds. In Stall mode and Nonblocking mode, the processor fetches an instruction from the ITR when an ITR write succeeds.

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