| Copyright © 2006-2009 ARM Limited. All rights reserved. | ARM DDI 0344I |
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The processor takes a debug exception when a software debug event occurs while in Monitor debug-mode. Prefetch Abort and Data Abort Vector catch debug events are ignored though.
If the processor takes a debug exception because of a breakpoint, BKPT, or vector catch debug event, the processor performs the following actions:
Sets the DSCR[5:2] method of entry bits to indicate that a watchpoint occurred.
Sets the CP15 IFSR and IFAR registers as described in Effect of debug exceptions on CP15 registers and WFAR.
Performs the same sequence of actions as in a Prefetch Abort exception by:
updating the SPSR_abt with the saved CPSR
changing the CPSR to abort mode and ARM state with normal interrupts and imprecise aborts disabled
setting R14_abt as a regular Prefetch Abort exception,
that is, this register gets the address of the cancelled instruction
plus 0x04
setting the PC to the appropriate Prefetch Abort vector.
The Prefetch Abort handler checks the IFSR bit to determine if a debug exception or other kind of Prefetch Abort exception causes the exception entry. If the cause is a debug exception, the Prefetch Abort handler must branch to the debug monitor. You can find the address of the instruction to restart in the R14_abt register.
If the processor takes a debug exception because of a watchpoint debug event, the processor performs the following actions:
sets the DSCR[5:2] method of debug entry bits to the Precise Watchpoint Occurred encoding
sets the CP15 DFSR, FAR, and WFAR registers as described in Effect of debug exceptions on CP15 registers and WFAR
performs the same sequence of actions as in a Data Abort exception by:
updating the SPSR_abt with the saved CPSR
changing the CPSR to abort mode and ARM state with normal interrupts and imprecise aborts disabled
setting R14_abt as a regular Data Abort exception,
that is, this register gets the address of the cancelled instruction
plus 0x08
setting the PC to the appropriate Data Abort vector.
The Data Abort handler checks the DFSR bits to determine if the exception entry was caused by a Debug exception or other kind of Data Abort exception. If the cause is a Debug exception, the Data Abort handler must branch to the debug monitor. The address of the instruction to restart can be found in the R14_abt register.
Table 12.53 shows the values in the Link Register after exceptions. The ARM and Thumb columns in this table represent the processor state in which the exception occurred.
Table 12.53. Values in Link Register after exceptions
| Cause of fault | ARM | Thumb | Return address (RA) meaning |
|---|---|---|---|
| Breakpoint | RA+4 | RA+4 | Breakpointed instruction address |
| Watchpoint | RA+8 | RA+8 | Address of the instruction that triggered the watchpoint event |
| BKPT instruction | RA+4 | RA+4 | BKPT instruction address |
| Vector catch | RA+4 | RA+4 | Vector address |
| Prefetch Abort | RA+4 | RA+4 | Address of the instruction that the prefetch abort event canceled |
| Data Abort | RA+8 | RA+8 | Address of the instruction that the data abort event canceled |
| Copyright © 2006-2009 ARM Limited. All rights reserved. | ARM DDI 0344I |
| Non-Confidential | |
| PDF version | |
| Home > Debug > Debug exception |