12.8.8. Exceptions in debug state

While in debug state, exceptions are handled as follows:

Reset

This exception is taken as in normal processor state. This means the processor leaves debug state as a result of the system reset.

Prefetch Abort

This exception cannot occur because the processor does not fetch any instructions while in debug state.

Debug

The processor ignores debug events, including BKPT instruction.

SVC

The processor ignores SVC exceptions.

SMC

The processor ignores SMC exceptions.

Undefined

When an Undefined Instruction exception occurs in debug state, the behavior of the core is as follows:

  • PC, CPSR, SPSR_und, and R14_und are unchanged

  • the processor remains in debug state

  • DSCR[8], sticky undefined bit, is set to 1.

Precise Data abort

When a precise Data Abort occurs in debug state, the behavior of the core is as follows:

  • PC, CPSR, SPSR_abt, and R14_abt are unchanged

  • the processor remains in debug state

  • DSCR[6], sticky precise data abort bit, is set to 1

  • DFSR and FAR are set to the same values as if the abort had occurred in normal state.

Imprecise Data Abort

When an imprecise Data Abort occurs in debug state, the behavior of the core is as follows, regardless of the setting of the CPSR A bit:

  • PC, CPSR, SPSR_abt, and R14_abt are unchanged

  • the processor remains in debug state

  • DSCR[7], sticky imprecise data abort bit, is set to 1

  • the imprecise Data Abort does not cause the processor to perform an exception entry sequence so DFSR remains unchanged

  • the processor does not act on this imprecise Data Abort on exit from the debug state, that is, the imprecise abort is discarded.

Imprecise Data Aborts on entry and exit from debug state

The processor performs an implicit Data Synchronization Barrier (DSB) operation as part of the debug state entry sequence. If this operation detects an imprecise Data Abort, the processor records this event and its type as if the CPSR A bit was set to 1. The purpose of latching this event is to ensure that it can be taken on exit from debug state.

If the processor detects an imprecise Data Abort while already in debug state, for example a debugger-generated imprecise abort, the processor sets the sticky imprecise Data Abort bit, DSCR[7], to 1 but otherwise it discards it. The act of discarding these debugger-generated imprecise Data Aborts does not affect recorded application-generated imprecise Data Aborts.

Before forcing the processor to leave debug state, the debugger must execute a DSB sequence to ensure that all debugger-generated imprecise Data Aborts are detected, and therefore discarded, while still in debug state. After exiting debug state, the processor acts on any recorded imprecise Data Aborts as indicated by the CPSR A bit.

Imprecise Data Aborts and watchpoints

The watchpoint exception has a higher priority than an imprecise Data Abort. If a data access causes both a watchpoint and an imprecise Data Abort, the processor enters debug state before taking the imprecise Data Abort. The imprecise Data Abort is recorded. This priority order ensures correct behavior where invasive debug is not permitted in privileged modes.

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