14.3. ETM register summary

The ETM registers are defined in the ETM Architecture Specification.

Table 14.2 shows the values of the Identification registers and the Integration registers that are implementation-defined and are not described in the ETM Architecture Specification.

Table 14.2. ETM register summary

Register nameBase offset[1]TypeReset valueDescription
Configuration Code0x004R0x8D294024Configuration Code Register
ID0x1E4R0x410CF236ID Register
Configuration Code Extension0x1E8R0x000008A2Configuration Code Extension Register
ITMISCOUT0xEDCW-ITMISCOUT Register
ITMISCIN0xEE0R-[2]ITMISCIN Register
ITTRIGGER0xEE8W-ITTRIGGER Register
ITATBDATA00xEECW-ITATBDATA0 Register
ITATBCTR20xEF0R-bITATBCTR2 Register
ITATBCTR10xEF4W-ITATBCTR1 Register
ITATBCTR00xEF8W-ITATBCTR0 Register
PeripheralID40xFD0R0x00000004Peripheral Identification Registers
PeripheralID50xFD4R0x00000000
PeripheralID60xFD8R0x00000000
PeripheralID70xFDCR0x00000000
PeripheralID00xFE0R0x00000021
PeripheralID10xFE4R0x000000B9
PeripheralID20xFE8R0x0000006B
PeripheralID30xFECR0x00000010
ComponentID00xFF0R0x0000000DComponent Identification Registers
ComponentID10xFF4R0x00000090
ComponentID20xFF8R0x00000005
ComponentID30xFFCR0x000000B1

[1] The value given in the Base offset column is the address offset for memory-mapped access. To get the register number used in the ETM Architecture Specification, divide this offset by four.

[2] The values of these read-only registers depend on the signals on external pins of the ETM. Therefore it is not possible to define the register reset values.


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