14.4.6. Integration Test Registers

The following sections describe the Integration Test Registers. To access these registers you must first set bit [0] of the Integration Mode Control Register to 1.

See the ETM Architecture Specification for more information.

Table 14.8. Output signals that can be controlled by the Integration Test Registers

SignalRegisterBitDescription
AFREADYMITATBCTR0[1]See ITATBCTR0 Register
ATBYTESM[1:0]ITATBCTR0[9:8]See ITATBCTR0 Register
ATDATAM[31, 23, 15, 7, 0]ITATBDATA0[4:0]See ITATBDATA0 Register
ATIDM[6:0]ITATBCTR1[6:0]See ITATBCTR1 Register
ATVALIDMITATBCTR0[0]See ITATBCTR0 Register
EXTOUT[1:0]ITMISCOUT[9:8]See ITMISCOUT Register
TRIGGERITTRIGGER[0]See ITTRIGGER Register

Table 14.9. Input signals that can be read by the Integration Test Registers

SignalRegisterBitDescription
AFVALIDMITATBCTR2[1]ITATBCTR2 Register
ATREADYMITATBCTR2[0]ITATBCTR2 Register
DBGACKITMISCIN[4]ITMISCIN Register
EXTIN[3:0]ITMISCIN[3:0]ITMISCIN Register

Using the Integration Test Registers

The CoreSight Design Kit Technical Reference Manual gives a full description of the use of the Integration Test Registers to check integration. In brief, when bit [0] of the Integration Mode Control Register is set to 1:

  • Values written to the write-only Integration Test Registers map onto the specified outputs of ETM. For example, writing 0x3 to ITMISCOUT[1:0] causes EXTOUT[1:0] to take the value 0x3.

  • Values read from the read-only integration test registers correspond to the values of the specified inputs of ETM. For example, if you read ITMISCIN[1:0] you obtain the value of EXTIN.

ITMISCOUT Register

The ITMISCOUT Register, miscellaneous outputs, at offset 0xEDC, is write-only. This register controls signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.6 shows the bit arrangement of the ITMISCOUT Register.

Figure 14.6. ITMISCOUT Register format


Table 14.10 shows how the bit values correspond with the ITMISCOUT Register functions.

Table 14.10. ITMISCOUT Register bit functions

BitsFieldFunction
[31:2]-Reserved, SBZ
[1:0]EXTOUTDrives the EXTOUT[1:0] outputs

ITMISCIN Register

The ITMISCIN Register, miscellaneous inputs, at offset 0xEE0, is read-only. This register enables the values of signal inputs to be read when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.7 shows the bit arrangement of the ITMISCIN Register.

Figure 14.7. ITMISCIN Register format


Table 14.11 shows how the bit values correspond with the ITMISCIN Register functions. The value of these fields depend on the signals on the input pins when the register is read.

Table 14.11. ITMISCIN Register bit functions

BitsFieldFunction
[31:5]-Reserved, RAZ
[4]DBGACKReturns the value of the DBGACK input
[3:0]EXTINReturns the value of the EXTIN[3:0] inputs

ITTRIGGER Register

The ITTRIGGER Register, trigger request, at offset 0xEE8, is write-only. This register controls the signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.8 shows the bit arrangement of the ITTRIGGER Register.

Figure 14.8. ITTRIGGER Register format


Table 14.12 shows how the bit values correspond with the ITTRIGGER Register functions.

Table 14.12. ITTRIGGER Register bit functions

BitsFieldFunction
[31:1]-Reserved, SBZ
[0]TRIGGERDrives the TRIGGER output

ITATBDATA0 Register

The ITATBDATA0 Register, ATB data 0, at offset 0xEEC, is write-only. This register controls signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.9 shows the bit assignment of the ITATBDATA0 Register.

Figure 14.9. ITATBDATA0 Register format


Table 14.13 shows how the bit values correspond with the ITATBDATA0 Register functions.

Table 14.13. ITATBDATA0 Register bit functions

BitsFieldFunction
[31:5]-Reserved, SBZ
[4:0]ATDATAMDrives the ATDATAM[31, 23, 15, 17, 0] outputs

ITATBCTR2 Register

The ITATBCTR2 Register, ATB control 2, at offset 0xEF0, is read-only. This register enables the values of signal inputs to be read when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.10 shows the bit assignment of the ITATBCTR2 Register.

Figure 14.10. ITATBCTR2 Register format


Table 14.14 shows how the bit values correspond with the ITATBCTR2 Register functions. The value of these fields depend on the signals on the input pins when the register is read.

Table 14.14. ITATBCTR2 Register bit functions

BitsFieldFunction
[31:2]-Reserved, RAZ
[1]AFVALIDMReturns the value of the AFVALIDM input
[0]ATREADYMReturns the value of the ATREADYM input

ITATBCTR1 Register

The ITATBCTR1 Register, ATB control 1, at offset 0xEF4, is write-only. This register controls signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.11 shows the bit assignment of the ITATBCTR1 Register.

Figure 14.11. ITATBCTR1 Register format


Table 14.15 shows how the bit values correspond with the ITATBCTR1 Register functions.

Table 14.15. ITATBCTR1 Register bit functions

BitsFieldFunction
[31:7]-Reserved, SBZ
[6:0]ATIDMDrives the ATIDM[6:0] outputs

ITATBCTR0 Register

The ITATBCTR0 Register, ATB control 0, at offset 0xEF8, is write-only. This register controls signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 14.12 shows the bit assignment of the ITATBCTR0 Register.

Figure 14.12. ITATBCTR0 Register format


Table 14.16 shows how the bit values correspond with the ITATBCTR0 Register functions.

Table 14.16. ITATBCTR0 Register bit functions

BitsFieldFunction
[31:10]-Reserved, SBZ
[9:8]ATBYTESMDrives the ATBYTESM[1:0] outputs
[7:2]-Reserved, SBZ
[1]AFREADYMDrives the AFREADYM output
[0]ATVALIDMDrives the ATVALIDM output

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