3.2.81. c15, L2 system array debug data registers

The purpose of the L2 system array debug data registers is to hold the data:

Because the L2 data arrays are greater than 32-bits wide, the processor contains three registers, Data 0, Data 1, and Data 2 registers, to hold data when retrieving or registering data as a result of read/write operations. If the data is greater than 32-bit wide, all of the registers are used to transfer data.

The Data 0, Data 1, and Data 2 read/write registers are accessible in secure privileged modes only.

To access the L2 system debug registers, read or write CP15 with:

MCR p15, 0, <Rd>, c15, c8, 0 ; Write L2 Data 0 Register
MRC p15, 0, <Rd>, c15, c8, 0 ; Read L2 Data 0 Register
MCR p15, 0, <Rd>, c15, c8, 1 ; Write L2 Data 1 Register
MRC p15, 0, <Rd>, c15, c8, 1 ; Read L2 Data 1 Register
MCR p15, 0, <Rd>, c15, c8, 5 ; Write L2 Data 2 Register
MRC p15, 0, <Rd>, c15, c8, 5 ; Read L2 Data 2 Register

Figure 3.81 shows the bit arrangement of the L2 Data 0 Register when retrieving or registering data as a result of the read/write operations.

Figure 3.81. L2 Data 0 Register format


Figure 3.82 shows the bit arrangement of the L2 Data 1 Register when retrieving or registering data as a result of the read/write operations.

Figure 3.82. L2 Data 1 Register format


Figure 3.83 shows the bit arrangement of the L2 Data 2 Register when retrieving or registering data as a result of the read/write operations.

Figure 3.83. L2 Data 2 Register format


Table 3.158 shows how the bit values correspond with the L2 Data 0 Register functions as a result of an L2 parity/ECC read/write operation.

Table 3.158. Functional bits of L2 Data 0 Register for an L2 parity/ECC operation

BitsFieldFunction
[31:16]-Reserved. UNP, SBZ.
[15:0]DataHolds L2 parity/ECC information.

To perform an L2 parity/ECC operation, read or write CP15 with:

MCR p15, 0, c15, c8, 4 ; L2 parity and ECC write
MCR p15, 0, c15, c9, 4 ; L2 parity and ECC read

Table 3.159 shows how the bit values correspond with the L2 Data 0 Register functions as a result of an L2 tag RAM read/write operation.

Table 3.159. Functional bits of L2 Data 0 Register for a tag RAM operation

BitsFieldFunction
[31:13]DataHolds bits [31:13] of the physical address tag read from or written to the L2 tag RAM.
[12:8]-Reserved. UNP, SBZ.
[7:5]Data

Bit [7] holds the L2 tag RAM parity. Bits [6:5] hold the L2 tag RAM outer attributes.

[4:2]-Reserved. UNP, SBZ.
[1:0]Data

Bit [1] holds the L2 tag RAM secure valid bit and bit [0] holds the nonsecure valid bit.


To perform an L2 tag RAM operation, read or write CP15 with:

MCR p15, 0, c15, c8, 2 ; L2 tag write
MCR p15, 0, c15, c9, 2 ; L2 tag read

Table 3.160 shows how the bit values correspond with the L2 Data 0 Register functions as a result of an L2 data RAM read/write operation.

Table 3.160. Functional bits of L2 Data 0 Register for a data RAM operation

BitsFieldFunction
[31:0]DataHolds L2 data RAM information

Table 3.161 shows how the bit values correspond with the L2 Data 1 Register as a result of a data RAM read/write operation.

Table 3.161. Functional bits of L2 Data 1 Register for a data RAM operation

BitsFieldFunction
[31:0]DataHolds L2 data RAM information

Table 3.162 shows how the bit values correspond with the L2 Data 2 Register as a result of a data RAM read/write operation.

Table 3.162. Functional bits of L2 Data 2 Register for a data RAM operation

BitsFieldFunction
[31:1]-Reserved. UNP, SBZ.
[0]DataHolds a duplicate copy of the dirty bit that the L2 tag RAM stores.

To perform an L2 data 0, data 1, or data 2 operation, read or write CP15 with:

MCR p15, 0, c15, c8, 0 ; L2 data 0 write
MRC p15, 0, c15, c8, 0 ; L2 data 0 read
MCR p15, 0, c15, c8, 1 ; L2 data 1 write
MRC p15, 0, c15, c8, 1 ; L2 data 1 read
MCR p15, 0, c15, c8, 5 ; L2 data 2 write
MRC p15, 0, c15, c8, 5 ; L2 data 2 read
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