13.4. System registers

The VFPv3 architecture describes the following system registers:

Table 13.5 shows the NEON and VFP system registers.

Table 13.5. NEON and VFP system registers

RegisterFMXR/FMRX <reg> fieldAccess typeReset state
Floating-Point System ID Register, FPSIDb0000Read-only0x410330c3
Floating-Point Status and Control Register, FPSCRb0001Read/write0x00000000
Floating-Point Exception Register, FPEXCb1000Read/write0x00000000
Media and VFP Feature Register 0, MVFR0b0111Read-only0x11110222
Media and VFP Feature Register 1, MVFR1b0110Read-only0x00011111

Note

The FPSID, MVFR0, and MVFR1 Registers are read-only. Attempts to write these registers are ignored.

Table 13.6 shows the processor modes for accessing the NEON and VFP system registers.

Table 13.6. Accessing NEON and VFP system registers

RegisterPrivileged accessUser access
 FPEXC.EN=0FPEXC.EN=1FPEXC.EN=0FPEXC.EN=1
FPSIDPermittedPermittedNot permittedNot permitted
FPSCRNot permittedPermittedNot permittedPermitted
MVFR0, MVFR1PermittedPermittedNot permittedNot permitted
FPEXCPermittedPermittedNot permittedNot permitted

Table 13.6 shows that a privileged mode is sometimes required to access a NEON and VFP system register. When a privileged mode is required, an instruction that tries to access a register in a nonprivileged mode takes the Undefined Instruction trap.

For a NEON or VFP system register to be accessible, it must follow the rules in Table 13.6 and it must also be accessible by the Coprocessor Access Control Register and the Nonsecure Access Control Register. See c1, Coprocessor Access Control Register and c1, Nonsecure Access Control Register for more information.

Note

All hardware ID information is now privileged access only.

FPSID is privileged access only

This is a change in VFPv3. In VFPv2 implementation, the FPSID register can be accessed in all modes.

MVFR registers are privileged access only

User code must issue a system call to determine what features are supported.

The following sections describe the NEON and VFP system registers:

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