17.8. Miscellaneous signals

Table 17.8 shows the setup and hold times of miscellaneous signals not described in the previous sections.

Table 17.8. Timing parameters of miscellaneous signals

SignalClockSetup parameterPercent of clock period Hold parameter
nPORESET[1],[2]CLK---
ARESETn[1],[2]CLK---
ARESETNEONn[1],[2]CLK---
L1RSTDISABLE[3]CLK---
L2RSTDISABLE[3]CLK---
CLKSTOPREQCLK---
CLKSTOPACKCLKTovclkstopack30%Tohclkstopack
SECMONOUTEN[4]CLK---
SECMONOUT[86:0]CLKTovsecmonout30%Tohsecmonout
STANDBYWFICLKTovstandbywfi30%Tohstandbywfi
nFIQ[1]CLK---
nIRQ[1]CLK---
VINITHI[3]CLK---
CFGTE[3]CLK---
CFGEND0[3]CLK---
CFGNMFI[3]CLK---
CP15SDISABLECLK---
CPEXIST[13:0][3]CLK---
SILICONID[31:0][3]CLK---
nPMUIRQ[1]CLKTovnpmuirq30%Tohnpmuirq

[1] This signal has multiple end-points and must be treated as level-sensitive.

[2] Figure 10.6 shows how this signal must be set up.

[3] This is a static input to the processor.

[4] This signal is sampled only during reset.


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