14.9. Idle state control

The ETM implements an idle state that must be entered before you can power down the ETM. Before entry to the idle state, the following sequence occurs:

  1. Trace is turned off.

  2. The ETM waits for all trace that has already been generated to reach the FIFO.

  3. The main FIFO is emptied.

  4. The resynchronizing FIFO is emptied.

  5. The ETM waits for any remaining trace on the ATB interface to be accepted.

  6. The resynchronizing FIFO sets the read and write pointers that is uses to zero.

When in idle state, you can safely remove the power from the ck_gclke or ATCLK domain. It is recommended that you use the OS Save and Restore Registers to save the registers in the ck_gclke domain before removing the power and to restore the registers after restoring the power. See the ETM Architecture Specification for more information.

Following a reset of the ck_gclke domain, the ETM is in idle state. The ETM is also in idle state when any of the following occur:

The ETM Status Register reports the programming bit as set to 1 if both:

The standard method to turn off the ETM is to set the programming bit to 1 and wait for the ETM Status Register to report the programming bit as set to 1. This method ensures that the idle entry sequence is complete before you can perform more operations.

If the idle request is cancelled before the idle entry sequence is complete, the ETM behaves as if the idle request is maintained until the idle entry sequence is complete. For example, if the programming bit is set to 1 and 0 in quick succession without checking the ETM Status Register, the programming bit is not cleared to 0 internally until the idle entry sequence has completed.

When a WFI occurs, the processor waits for the idle entry sequence to complete before stopping the clock to the ETM.

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