17.4. APB interface and miscellaneous debug signals

Table 17.4 shows the setup and hold times for:

PCLK is the clock for the APB interface and some miscellaneous debug signals, and CLK is the clock for all other miscellaneous debug signals.

Table 17.4. Timing parameters of APB interface and miscellaneous debug signals

SignalClockSetup parameterPercent of clock periodHold parameter
COMMRX[1]CLKTovcommrx30%Tohcommrx
COMMTX[1]CLKTovcommtx30%Tohcommtx
DBGACKCLKTovdbgack30%Tohdbgack
DBGNOCLKSTOPCLKTisdbgnoclkstop30%Tihdbgnoclkstop
DBGROMADDR[31:12][2]CLKTisdbgromaddr30%Tihdbgromaddr
DBGROMADDRV[2]CLKTisdbgromaddrv30%Tihdbgromaddrv
DBGSELFADDR[31:12][2]CLKTisdbgselfaddr30%Tihdbgselfaddr
DBGSELFADDRV[2]CLKTisdbgselfaddrv30%Tihdbgselfaddrv
EDBGRQ[1]PCLK---
DBGENPCLK---
DBGOSLOCKINIT[2]PCLKTisdbgoslockinit30%Tihdbgoslockinit
DBGNOPWRDWN[1]PCLKTovdbgnopwrdwn30%Tohdbgnopwrdwn
DBGPWRDWNREQ[1]PCLK---
ETMPWRDWNREQ[1],[3]PCLK---
DBGPWRDWNACKPCLKTovdbgpwrdwnack30%Tohdbgpwrdwnack
ETMPWRDWNACK[3]PCLKTovetmpwrdwnack30%Tohetmpwrdwnack
PRESETn[1],[4]PCLK---
PCLKENPCLKTispclken30%Tihpclken
PADDR31PCLKTispaddr3130%Tihpaddr31
PADDR11TO2[11:2]PCLKTispaddr11to230%Tihpaddr11to2
PENABLEPCLKTispenable30%Tihpenable
PSELCTI[5]PCLKTispselcti30%Tihpselcti
PSELDBGPCLKTispseldbg30%Tihpseldbg
PSELETM[4]PCLKTispseletm30%Tihpseletm
PWRITEPCLKTispwrite30%Tihpwrite
PRDATA[31:0]PCLKTovprdata30%Tohprdata
PWDATA[31:0]PCLKTispwdata30%Tihpwdata
PREADYPCLKTovpready30%Tohpready
PSLVERRPCLKTovpslverr30%Tohpslverr
NIDEN[1]PCLK---
SPIDEN[1]PCLK---
SPNIDEN[1]PCLK---

[1] This signal has multiple end-points and must be treated as level-sensitive.

[2] This is a static input to the processor.

[3] This signal is not required because debug and the ETM use the same power domain.

[4] Figure 10.6 shows how this signal must be set up.

[5] This signal is not present when the processor is configured without the ETM.


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