3.2.23. c0, Cache Size Identification Registers

The purpose of these registers is to provide cache size information for up to eight levels of cache containing instruction, data, or unified caches. The processor contains L1 and L2 cache. The Cache Size Selection Register determines which Cache Size Identification Register to select.

The Cache Size Identification Registers are:

Figure 3.18 shows the bit arrangement of the Cache Size Identification Register.

Figure 3.18. Cache Size Identification Register format


Table 3.41 shows how the bit values correspond with the Cache Size Identification Register functions. See Table 3.42 for valid bit field encodings.

Table 3.41. Cache Size Identification Register bit functions

BitsFieldFunction

[31]

WT

Indicates support available for write-through:

0 = write-through not supported

1 = write-through supported.

[30]

WB

Indicates support available for write-back:

0 = write-back not supported

1 = write-back supported.

[29]

RA

Indicates support available for read allocation:

0 = read allocation not supported

1 = read allocation supported.

[28]

WA

Indicates support available for write allocation:

0 = write allocation not supported

1 = write allocation supported.

[27:13]

NumSets

Indicates number of sets - 1.

[12:3]

Associativity

Indicates number of ways - 1.

[2:0]

LineSize

Indicates (log2(number of words in cache line)) - 2.


Table 3.42 shows the individual bit field and complete register encodings for the Cache Size Identification Register. Use this to match the cache size and level of cache set by the Cache Size Selection Register (CSSR). See c0, Cache Size Selection Register.

Table 3.42. Encodings of the Cache Size Identification Register

CSSRSizeComplete register encodingRegister bit field encoding
   WTWBRAWANumSetsAssociativityLineSize
0x016KB0xE007E01A11100x003F0x30x2
32KB0xE00FE01A11100x007F0x30x2
0x116KB0x2007E01A00100x003F0x30x2
32KB0x200FE01A00100x007F0x30x2
0x20KB0xF000000011110x00000x00x0
128KB0xF01FE03A11110x00FF0x70x2
256KB0xF03FE03A11110x01FF0x70x2
512KB0xF07FE03A11110x03FF0x70x2
1024KB0xF0FFE03A11110x07FF0x70x2
0x3-0xF-0x0Reserved

Table 3.43 shows the results of attempted access for each mode.

Table 3.43. Results of access to the Cache Size Identification Register[21]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[21] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Cache Size Identification Register, read CP15 with:

MRC p15, 1, <Rd>, c0, c0, 0; Cache Size Identification Register
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