13.4.4. Media and VFP Feature Registers, MVFR0 and MVFR1

The Media and VFP Feature Registers, MVFR0 and MVFR1, describe the features supported by the NEON and VFP coprocessor. These registers are accessible in privileged modes only.

Figure 13.6 shows the bit arrangement of the MVFR0 Register.

Figure 13.6. MVFR0 Register format


Table 13.11 shows how the bit values correspond with the MVFR0 Register functions.

Table 13.11. MVFR0 Register bit functions

BitsFieldFunction

[31:28]

RM

All VFP rounding modes supported:

0x1

[27:24]

SV

VFP short vector supported:

0x1

[23:20]

SR

VFP hardware square root supported:

0x1

[19:16]

D

VFP hardware divide supported:

0x1

[15:12]

TE

Only untrapped exception handling can be selected:

0x0

[11:8]

DP

Double precision supported in VFPv3:

0x2

[7:4]

SP

Single precision supported in VFPv3:

0x2

[3:0]

RB

32x64-bit media register bank supported:

0x2


Figure 13.7 shows the bit arrangement of the MVFR1 Register.

Figure 13.7. MVFR1 Register format


Table 13.12 shows how the bit values correspond with the MVFR1 Register.

Table 13.12. MVFR1 Register bit functions

BitsFieldFunction

[31:20]

-

Reserved

[19:16]

SP

Single precision floating-point instructions supported for NEON:

0x1

[15:12]

I

Integer instructions supported for NEON:

0x1

[11:8]

LS

Load/store instructions supported for NEON:

0x1

[7:4]

DN

Propagation of NaN values supported for VFP:

0x1

[3:0]

FZ

Full denormal arithmetic supported for VFP:

0x1


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