15.6.1. CTI Control Register, CTICONTROL

CTICONTROL is a read/write register that enables the CTI. Figure 15.4 shows the bit arrangement of the CTICONTROL Register.

Figure 15.4. CTI Control Register format


Table 15.4 shows how the bit values correspond with the CTICONTROL Register functions.

Table 15.4. CTI Control Register bit functions

BitsFieldFunction

[31:1]

-

Reserved. RAZ, SBZ.

[0]

GLBEN

Enables or disables the CTI:

0 = disable CTI (reset)

1 = enable CTI.

When disabled, all cross triggering mapping logic functionality is disabled for this processor.


Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential