3.2.54. c9, L2 Cache Lockdown Register

The L2 Cache Lockdown Register controls the L2 cache lockdown. The Lockdown Format C provides a method to restrict the replacement algorithm on cache linefills to only use selected cache ways within a set. Using this method, you can fetch or load code into the L2 cache and protect data from being evicted, or you can use the method to reduce cache pollution.

The L2 Cache Lockdown Register is:

Figure 3.48 shows the bit arrangement of the L2 Cache Lockdown Register.

Figure 3.48. L2 Cache Lockdown Register format


Table 3.106 shows how the bit values correspond with the L2 Cache Lockdown Register functions.

Table 3.106. L2 Cache Lockdown Register bit functions

Bits

Field

Function

[31:8]

-Reserved. UNP, SBZP.
[7]

LOCK

way-7

Lockdown bit for way 7 of the L2 cache:

0 = way 7 is not locked and allocation is determined by standard replacement algorithm

1 = way 7 is locked and no allocation is performed to this cache way.

[6]

LOCK

way-6

Lockdown bit for way 6 of the L2 cache:

0 = way 6 is not locked and allocation is determined by standard replacement algorithm

1 = way 6 is locked and no allocation is performed to this cache way.

[5]

LOCK

way-5

Lockdown bit for way 5 of the L2 cache:

0 = way 5 is not locked and allocation is determined by standard replacement algorithm

1 = way 5 is locked and no allocation is performed to this cache way.

[4]

LOCK

way-4

Lockdown bit for way 4 of the L2 cache:

0 = way 4 is not locked and allocation is determined by standard replacement algorithm

1 = way 4 is locked and no allocation is performed to this cache way.

[3]

LOCK

way-3

Lockdown bit for way 3 of the L2 cache:

0 = way 3 is not locked and allocation is determined by standard replacement algorithm

1 = way 3 is locked and no allocation is performed to this cache way.

[2]

LOCK

way-2

Lockdown bit for way 2 of the L2 cache:

0 = way 2 is not locked and allocation is determined by standard replacement algorithm

1 = way 2 is locked and no allocation is performed to this cache way.

[1]

LOCK

way-1

Lockdown bit for way 1 of the L2 cache:

0 = way 1 is not locked and allocation is determined by standard replacement algorithm

1 = way 1 is locked and no allocation is performed to this cache way.

[0]

LOCK

way-0

Lockdown bit for way 0 of the L2 cache:

0 = way 0 is not locked and allocation is determined by standard replacement algorithm

1 = way 0 is locked and no allocation is performed to this cache way.


Table 3.107 shows the results of attempted access for each mode.

Table 3.107. Results of access to the L2 Cache Lockdown Register[44]

 Secure privilegedNonsecure privilegedSecure UserNonsecure User
CL bit valueReadWriteReadWriteReadWriteReadWrite
0DataDataUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
1DataDataDataDataUndefinedUndefinedUndefinedUndefined

[44] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the L2 Cache Lockdown Register, read or write CP15 with:

MRC p15, 1, <Rd>, c9, c0, 0 ; Read L2 Cache Lockdown Register
MCR p15, 1, <Rd>, c9, c0, 0 ; Write L2 Cache Lockdown Register

Specific loading of addresses into cache way

The following procedure for lock down into a data or an instruction cache way i, with N cache ways, using Format C, ensures that only the target cache way i is locked down.

This is the architecturally-defined method for locking data into caches:

  1. Disable interrupts to ensure that no processor exceptions can occur during the execution of this procedure. If this is not possible, all code and data that any exception handlers can call must meet the conditions specified in step 2 and step 3.

  2. Ensure that all data that the following code uses, apart from the data that is to be locked down, is either:

    • in a noncacheable area of memory

    • in an already locked cache way.

  3. Ensure that the data to be locked down is in a cacheable area of memory.

  4. Ensure that the data to be locked down is not already in the cache, using either:

    • cache clean

    • invalidate

    • cache clean and invalidate.

    See c7, Cache operations.

  5. Enable allocation to the target cache way by writing to the Instruction or Data Cache Lockdown Register, with the CRm field set to 0, setting L to 0 for bit i, and L to 1 for all other ways.

  6. Ensure that the memory cache line is loaded into the cache by using an LDR instruction to load a word from the memory cache line, for each of the cache lines to be locked down in cache way i.

  7. Write to the Instruction or Data Cache Lockdown Register, setting L to 1 for bit i and restore all the other bits to the previous values before this routine was started.

Cache unlock procedure

To unlock the lock down portion of the cache, write to register c9, setting L to 0 for each bit.

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