10.1. Clock domains

The processor has three major clock domains:


High speed core clock used to clock all major processor interfaces. The L1 memory system uses both the rising and falling edges of CLK. If the implemented design uses logic requiring the negative edge of the CLK signal, the duty cycle of CLK must be 50%. Figure 10.1 shows this.

Figure 10.1. CLK duty cycle

CLK controls the following units within the processor:

  • instruction fetch unit

  • instruction decode unit

  • instruction execute unit

  • load/store unit

  • L2 cache unit, including AXI interface

  • NEON unit

  • ETM unit, not including the ATB interface

  • debug logic, not including the APB interface.


The instruction fetch, instruction decode, instruction execute, load/store, and L2 cache are called the core or integer core.


APB clock that controls the debug interface for the processor. PCLK is asynchronous to CLK and ATCLK. PCLK controls the debug interface and logic in the PCLK domain.


ATB clock that controls the ATB interface for the processor. ATCLK is asynchronous to CLK and PCLK. ATCLK controls the ATB interface.


You can implement PCLK and ATCLK to be synchronous to CLK. You can also implement PCLK and ATCLK to run synchronously to each other.

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