13.4.2. Floating-Point Status and Control Register, FPSCR

FPSCR is a read/write register that can be accessed in both privileged and unprivileged modes. All bits described as DNM in Figure 13.4 are reserved for future expansion. They must be initialized to zeros. To ensure that these bits are not modified, code other than initialization code must use read/modify/write techniques when writing to FPSCR. Failure to observe this rule can cause Unpredictable results in future systems.

Figure 13.4 shows the bit arrangement of the FPSCR Register.

Figure 13.4. Floating-Point Status and Control Register format


Table 13.8 shows how the bit values correspond with the FPSCR Register functions.

Table 13.8. FPSCR Register bit functions

BitsFieldFunction
[31]NSet if comparison produces a less than result
[30]ZSet if comparison produces an equal result
[29]CSet if comparison produces an equal, greater than, or unordered result
[28]VSet if comparison produces an unordered result
[27]QCSaturation cumulative flag
[26]DNMDo Not Modify
[25]DNDefault NaN mode enable bit: 0 = default NaN mode disabled 1 = default NaN mode enabled.
[24]FZFlush-to-zero mode enable bit: 0 = flush-to-zero mode disabled 1 = flush-to-zero mode enabled.
[23:22]RMODERounding mode control field: b00 = round to nearest (RN) mod b01 = round towards plus infinity (RP) mode b10 = round towards minus infinity (RM) mode b11 = round towards zero (RZ) mode.
[21:20]STRIDESee Vector length and stride control
[19]DNMDo Not Modify
[18:16]LENSee Vector length and stride control
[15]IDEInput Subnormal exception enable bit
[14:13]DNMDo Not Modify
[12]IXEInexact exception enable bit
[11]UFEUnderflow exception enable bit
[10]OFEOverflow exception enable bit
[9]DZEDivision by Zero exception enable bit
[8]IOEInvalid Operation exception enable bit
[7]IDCInput Subnormal cumulative flag
[6:5]DNMDo Not Modify
[4]IXCInexact cumulative flag
[3]UFCUnderflow cumulative flag
[2]OFCOverflow cumulative flag
[1]DZCDivision by Zero cumulative flag
[0]IOCInvalid Operation cumulative flag

Vector length and stride control

FPSCR[18:16] is the LEN field and controls the vector length for VFP instructions that operate on short vectors. The vector length is the number of iterations in a short vector instruction.

FPSCR[21:20] is the STRIDE field and controls the vector stride. The vector stride is the increment value used to select the registers involved in the next iteration of the short vector instruction.

The rules for vector operation do not allow a vector to use the same register more than once. LEN and STRIDE combinations that use a register more than once produce Unpredictable results, as Table 13.9 shows. Some combinations that work normally in single-precision short vector instructions cause Unpredictable results in double-precision instructions.

Table 13.9. Vector length and stride combinations

LENVector lengthSTRIDEVector strideSingle-precision vector instructionsDouble-precision vector instructions
b0001b00-All instructions are scalarAll instructions are scalar
b0001b11-UnpredictableUnpredictable
b0012b001Work normallyWork normally
b0012b112Work normallyWork normally
b0103b001Work normallyWork normally
b0103b112Work normally

Unpredictable

b0114b001Work normallyWork normally
b0114b112Work normally

Unpredictable

b1005b001Work normally

Unpredictable

b1005b112UnpredictableUnpredictable
b1016b001Work normally

Unpredictable

b1016b112UnpredictableUnpredictable
b1107b001Work normally

Unpredictable

b1107b112UnpredictableUnpredictable
b1118b001Work normally

Unpredictable

b1118b112UnpredictableUnpredictable

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