10.2.2. Soft reset

The soft reset sequence is used to trace with ETM or debug across a reset event. By asserting only the ARESETn and ARESETNEONn signals, the reset domains controlled by nPORESET, ETM, and debug in particular, are not reset. Therefore, breakpoints and watchpoints are retained during a soft reset sequence. Figure 10.7 shows a soft reset sequence.

Figure 10.7. Soft reset timing


An additional reset is provided to control the NEON unit independently of the processor reset. This reset can be used to hold the NEON unit in a reset state so that the power to the NEON unit can be safely removed without placing any logic within the NEON unit in a different state. The reset cycle timing requirements for ARESETNEONn are identical to those for ARESETn. ARESETNEONn must be held for a minimum of eight CLK cycles when asserted to guarantee that the NEON unit has entered a reset state.

In addition, both ARESETn and ARESETNEONn are used to manage various power domains within the processor. See Power control for information on the management of these resets and power domains.

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