10.3.2. Static or leakage power management

The processor can accommodate many different levels of static, or leakage power management. All of these techniques are specific to a given implementation of the processor. Some possibilities that the processor can accommodate are:

Note

This technical reference manual does not document retention or the usage of multi-Vt. However, this manual describes the power domains, or islands that are supported and the methods that are required to manage those domains in a manner that has been validated within the processor.

To completely eliminate leakage power consumption in the processor, you must remove the power supplied to the processor. Before powering down, all architectural state must be saved to memory and the L1 data cache or L2 unified cache must be cleaned to the point of coherency. When powering up the processor, you must apply a complete reset sequence with software that restores the architectural state. The sequence takes significant time and energy to perform a full power-down of the processor.

To improve the response time of a power-down sequence, the processor supports several key features to minimize the response time and to reduce the leakage power consumption:

The processor supports many different power islands combinations, including a single monolithic power grid, resulting in a single power domain. The supported power domains are:

Figure 10.11 shows the supported power domains.

Figure 10.11. Power domains


When implementing the different power domains, the following modes of operation apply:

If all power domains are implemented, the power domains can be independently controlled to give eight combinations of power-up and power-down domains. However, only some power-up and power-down domain combinations are valid. These are shown in Table 10.2.

Table 10.2. Valid power domains

Integer coreDebug and ETMNEON

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From the power domains shown in Figure 10.11, the following voltage domains can be derived. Figure 10.12 shows this.

Figure 10.12. Voltage domains


The voltage domains represent the power supply distributions that might be required in the Cortex-A8 processor. These include:

Debug PCLK and ETM ATCLK

Connects to SoC debug power domain.

ETM CLK

Operates at the same voltage as the processor but exists in same power domain as debug.

NEON

Operates at the same voltage as the processor and can be powered down while the processor is running.

L2 RAMs

Supports retention in the L2 cache, and supports SRAM voltage.

L1 data cache RAMs

Supports retention in the L1 data cache, and supports SRAM voltage.

Other L1 RAMs

Supports SRAM voltage.

Integer core

All logic within the integer core, not including SRAMs.

Any or all of these voltage domains can be removed from the processor. However, the removal of those domains must comply with the supported power domain configurations listed in Table 10.2.

NEON power domain

If NEON is not required, you can reduce leakage by turning off the power to the NEON unit. While the NEON unit is powered down, any Advanced SIMD instructions executed take the Undefined Instruction exception. The OS uses the Undefined Instruction exception on an Advanced SIMD instruction as a signal to apply power to the NEON unit, if powered down, or to activate NEON, if disabled.

To enable NEON to be powered down, the implementation must place NEON on a separately controlled power supply. In addition, the outputs of NEON must be clamped to benign values while NEON is powered down, to indicate that NEON is idle.

Powering down the NEON power domain while the processor is in reset

To power down the NEON power domain while the processor is in reset, apply the following sequence:

  1. Assert both ARESETn and ARESETNEONn to place the processor in reset. You must assert ARESETn and ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.

  2. Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.

  3. Remove power from the NEON power domain.

  4. Deassert ARESETn, but continue to assert ARESETNEONn.

If the processor is executing a power-on reset sequence or is first powering up:

  1. Assert both ARESETn and ARESETNEONn. You must assert ARESETn and ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.

  2. Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.

  3. While keeping the NEON power domain off, supply power to the other active power domains.

  4. Deassert ARESETn, but continue to assert ARESETNEONn.

While ARESETNEONn remains asserted, all Advanced SIMD instructions cause an Undefined Instruction exception.

Note

If ARESETNEONn is deasserted or the NEON output clamps are released without following one of the specified NEON power-up sequences, the results are Unpredictable and might cause the processor to deadlock.

Powering down the NEON power domain while the processor is not in reset

To power down the NEON power domain while the processor is not in reset, the NEON power domain must be placed into an idle state. Apply the following sequence to place the NEON power domain into an idle state:

  1. Software must disable access to the NEON unit using the Coprocessor Access Control Register, see c1, Coprocessor Access Control Register. All outstanding Advanced SIMD instructions retire and all subsequent Advanced SIMD instruction cause an Undefined Instruction exception.

    MRC p15, 0, <Rd>, c1, c0, 2;    Read Coprocessor Access Control Register
    
    BIC <Rd>, <Rd>, #0xF00000;      Disable access to CP10 and CP11
    
    MCR p15, 0, <Rd>, c1, c0, 2;    Write Coprocessor Access Control Register
    
  2. Software must signal to the external system that the NEON unit is disabled.

  3. Assert ARESETNEONn to place NEON in reset. You must assert ARESETNEONn for at least eight CLK cycles before activating the NEON clamps.

  4. Activate the NEON output clamps by asserting the CLAMPNEONOUT input HIGH.

  5. Remove power from the NEON power domain.

Note

If ARESETNEONn is deasserted or the NEON output clamps are released without following one of the specified NEON power-up sequences, the results are Unpredictable and might cause the processor to deadlock.

Powering up the NEON power domain while the processor is in reset

To apply power to the NEON power domain while the processor is in reset, use the following sequence:

  1. Assert ARESETn and keep ARESETNEONn asserted.

  2. Apply power to the NEON power domain.

  3. Release the NEON output clamps by deasserting CLAMPNEONOUT.

  4. Deassert ARESETn and ARESETNEONn.

After the completion of the reset sequence, you can enable the NEON unit using the Coprocessor Access Control Register. See c1, Coprocessor Access Control Register.

Powering up the NEON power domain while the processor is not in reset

To apply power to the NEON power domain while the processor is not in reset, use the sequence that follows. With the NEON power domain currently powered down, it is assumed that ARESETNEONn is asserted.

  1. Software must disable access to the NEON unit using the Coprocessor Access Control Register, see c1, Coprocessor Access Control Register.

    MRC p15, 0, <Rd>, c1, c0, 2;    Read Coprocessor Access Control Register
    
    BIC <Rd>, <Rd>, #0xF00000;      Disable access to CP10 and CP11
    
    MCR p15, 0, <Rd>, c1, c0, 2;    Write Coprocessor Access Control Register
    
  2. Software must signal to the external system that it is safe to power up the NEON unit.

  3. Apply power to the NEON power domain.

  4. Deassert ARESETNEONn. NEON requires a minimum of 20 CLK cycles to complete its reset sequence. Therefore, the system must wait until NEON has completed its reset sequence before releasing the NEON clamps.

  5. Release the NEON output clamps by deasserting CLAMPNEONOUT.

  6. Software must poll the external system to determine that it is safe to enable the NEON unit.

After the completion of the reset sequence, you can enable the NEON unit using the Coprocessor Access Control Register. See c1, Coprocessor Access Control Register.

Debug and ETM power domains

If the core is running in an environment where debug facilities are not required, you can reduce leakage power by powering down the debug PCLK, ETM CLK, and ETM ATCLK power domains. Debug PCLK, ETM CLK, and ETM ATCLK power domains must be built using a common power supply.

Powering down the debug and ETM power domains

To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, the implementation must place debug PCLK, ETM CLK, and ETM ATCLK on a separately controlled and shared power supply. In addition, the outputs of debug PCLK, ETM CLK, and ETM ATCLK must be clamped to benign values while powered down to indicate that the interface is idle.

To power down the debug PCLK, ETM CLK, and ETM ATCLK power domains, apply the following sequence:

  1. Assert both PRESETn and ATRESETn. You must assert PRESETn for at least eight PCLK cycles and ATRESETn for at least eight ATCLK cycles before asserting CLAMPDBGOUT.

  2. Activate the debug PCLK, ETM CLK, and ETM ATCLK output clamps by asserting the CLAMPDBGOUT input HIGH.

  3. Remove power from the debug PCLK, ETM CLK, and ETM ATCLK power domains. PRESETn and ATRESETn must remain asserted while the domain is powered down.

Powering up the debug and ETM domains

To power up the debug PCLK, ETM CLK, and ETM ATCLK power domains, use the sequence that follows. It is assumed that both PRESETn and ATRESETn are asserted during the sequence.

  1. Apply power to the debug PCLK, ETM CLK, and ETM ATCLK power domains.

  2. Release the debug PCLK, ETM CLK, and ETM ATCLK output clamps by deasserting CLAMPDBGOUT.

  3. If the system uses the debug PCLK, ETM CLK, and ETM ATCLK hardware, it is safe to deassert either PRESETn, ATRESETn, or both.

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