10.3.1. Dynamic power management

The processor has many different dynamic power management facilities. The most common form of dynamic power management is control of the clock network within the processor.

The processor has three levels of clock gating to manage dynamic power. The levels correspond to the following functions:

Level 1

This is architectural gating, also known as Wait-For-Interrupt (WFI), or the CLKSTOPREQ and CLKSTOPACK signals on the Cortex-A8 processor.

Level 2

This is major function gating, such as NEON, ETM, or integer core gating.

Level 3

This is state element gating, such as local clock gating.

The processor contains all hardware necessary for architecture, unit, and local clock gating. No external hardware is required to clock gate the processor.

Wait-For-Interrupt architecture

Executing a Wait-For-Interrupt instruction puts the processor into a low-power state until one of the following occurs:

  • an IRQ or FIQ interrupt

  • a halting debug event when the DBGNOCLKSTOP signal is HIGH.

See Halting debug event for information on halting debug events.

Note

  • If you are debugging software running on the Cortex-A8 processor, DBGNOCLKSTOP must be HIGH. Otherwise, halting debug events do not work as architected and the APB interface does not return a response when accessing the ETM, CTI, or core domain debug registers. See Table 12.3 for information on which debug registers are in the core.

  • If DBGNOCLKSTOP is HIGH and you execute the Wait-For-Interrupt instruction, the processor goes into an idle state but not into a low-power state.

  • The STANDBYWFI pin remains HIGH even when DBGNOCLKSTOP is HIGH.

When executing the WFI instruction, the processor waits for the following events to complete before entering the idle or low-power state:

  • L1 data memory system loads and stores are complete

  • all L1 instruction memory system fetches are complete

  • all L2 memory system transactions are complete

  • all AXI interface transactions are complete

  • all Advanced SIMD instructions are complete

  • all ETM data transfers from core clock domain to ATB clock domain are complete

  • preloading engine, PLE, activity is interrupted.

On entry into the low-power state, the processor asserts the STANDBYWFI signal. Assertion of STANDBYWFI guarantees that the processor and the AXI interface are in the idle state. The APB PCLK clock domain and the ATB ATCLK clock domain can remain active.

Figure 10.9 shows the upper bound for the STANDBYWFI deassertion timing after assertion of nIRQ or nFIQ.

Figure 10.9. STANDBYWFI deassertion


Hardware clock stopping

Another form of architectural clock gating is controlled by the processor CLKSTOPREQ input. Asserting CLKSTOPREQ puts the processor into a low-power state until CLKSTOPREQ is deasserted.

Figure 10.10 shows the relationship between CLKSTOPREQ and CLKSTOPACK.

Figure 10.10. CLKSTOPREQ and CLKSTOPACK


When the system asserts CLKSTOPREQ, the processor waits for completion of the same events as in the Wait-For-Interrupt case before entering the low-power state. See Wait-For-Interrupt architecture for more information.

On entry into the low-power state, the processor asserts the CLKSTOPACK output. Assertion of CLKSTOPACK guarantees that the processor and the AXI interface are in idle state. The APB PCLK domain and the ATB ATCLK clock domain can remain active.

The number of cycles between CLKSTOPREQ and CLKSTOPACK assertion has a lower bound of 20 cycles but no upper bound. The upper bound is a function of the latency to access the slowest device mapped on the processor AXI bus and, therefore, is system-dependent. After the processor asserts CLKSTOPACK, it closes the architectural clock gate. However, eight CLK cycles must pass before you can rely on the architectural clock gate being completely closed.

Figure 10.10 shows the system stopping CLK after the architectural clock gate is closed. This enables additional energy savings, but it is optional. In addition, the supply voltage, Vdd (core) can also be lowered as shown in Figure 10.10 to improve energy savings. However, CLK must not stop before the architectural clock gate is closed, that is, it must continue to run for at least eight cycles after CLKSTOPACK is asserted.

After the architectural clock gate closes, the system can keep the processor in this low-power state for as long as required, by holding CLKSTOPREQ HIGH. When the system deasserts CLKSTOPREQ, this causes the architectural clock gate to open. The processor then responds by deasserting CLKSTOPACK and resuming instruction execution. The upper bound for the number of CLK cycles between CLKSTOPREQ and CLKSTOPACK deassertion is 8.

When driving CLKSTOPREQ, the system must comply with a set of protocol rules, otherwise the processor behavior is Unpredictable. The rules are as follows:

  • CLKSTOPREQ must not transition from LOW to HIGH if CLKSTOPACK is already HIGH.

  • When CLKSTOPREQ is HIGH, it must remain HIGH until CLKSTOPACK goes HIGH. Only when CLKSTOPACK goes HIGH can CLKSTOPREQ go LOW.

Note

  • If you are debugging software running on the Cortex-A8 processor, DBGNOCLKSTOP must be HIGH. Otherwise, halting debug events do not work as architected and the APB interface does not return a response when accessing the ETM, CTI, or core domain debug registers. See Table 12.3 for information on which debug registers are in the core.

  • If DBGNOCLKSTOP is HIGH and the system asserts CLKSTOPREQ, the processor goes into an idle state but not into a low-power state.

  • The CLKSTOPACK output pin remains HIGH even when DBGNOCLKSTOP is HIGH.

NEON or ETM unit level gating

In addition to the architectural gating mechanism, the processor supports gating of major components within the processor such as the NEON unit, VFP coprocessor, and ETM unit.

The cp10 and cp11 fields in the CP15 c1 Coprocessor Access Control Register control access to the NEON and VFP coprocessor. See c1, Coprocessor Access Control Register. Reset clears the cp10 and cp11 fields and disables the NEON and VFP clocks.

The ETM Control Register enables the ETM. See the Embedded Trace Macrocell Architecture Specification for more information. The global enable bit in the CTI Control Register enables the ETM clocks, excluding the ATB clock, ATCLK, which can only be gated external to the processor. See CTI Control Register, CTICONTROL.

DFF gating

The finest level of dynamic power control is at the Delay Flip-Flop (DFF) level. This is implicit to the design and requires no external support.

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