3.2.82. c15, L2 parity/ECC array operations

The purpose of the L2 parity/ECC array operations is to:

The L2 parity/ECC array operation is accessible in secure privileged mode only. You can determine the value of N in Figure 3.84 and Figure 3.85 from Table 3.163.

Figure 3.84 shows the bit arrangement of the L2 parity/ECC array read operation.

Figure 3.84. L2 parity/ECC array read operation format


The value of N in the Address field is:

Table 3.163. Address field values

L2 cache sizeN
0KB-
128KB13
256KB14
512KB15
1024KB16

Figure 3.85 shows the bit arrangement of the L2 parity/ECC array write operation.

Figure 3.85. L2 parity/ECC array write operation format


To write one entry to the L2 parity/ECC array, for example:

LDR R0, =0x0000ABCD;            
MCR p15, 0, R0, c15, c8, 0;     Move R0 to L2 Data 0 Register
LDR R1, =0x400000C0;            
MCR p15, 0, R1, c15, c8, 4;     Write L2 Data 0 Register to L2 parity/ECC RAM

To read one entry from the L2 parity/ECC array, for example:

LDR R1, =0x400000C0 ;           
MCR p15, 0, R1, c15, c9, 4;     Read L2 parity/ECC RAM into L2 Data 0 Register
MRC p15, 0, R2, c15, c8, 0;     Move L2 Data 0 Register to R2
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