17.2. AXI interface

Table 17.2 shows the setup and hold times for the AXI interface signals.

Table 17.2. Timing parameters of AXI interface

SignalClockSetup parameterPercent of clock periodHold parameter
A64n128[1]CLK---
ACLKENCLKTisaclken30%Tihaclken
ARADDR[31:0]CLKTovaraddr30%Toharaddr
ARBURST[1:0]CLKTovarburst30%Toharburst
ARCACHE[3:0]CLKTovarcache30%Toharcache
ARID[3:0]CLKTovarid30%Toharid
ARLEN[3:0]CLKTovarlen30%Toharlen
ARLOCK[1:0]CLKTovarlock30%Toharlock
ARPROT[2:0]CLKTovarprot30%Toharprot
ARSIZE[2:0]CLKTovarsize30%Toharsize
ARVALIDCLKTovarvalid30%Toharvalid
ARREADYCLKTisarready30%Tiharready
RDATA[127:0]CLKTisrdata30%Tihrdata
RID[3:0]CLKTisrid30%Tihrid
RLASTCLKTisrlast30%Tihrlast
RRESP[1:0]CLKTisrresp30%Tihrresp
RVALIDCLKTisrvalid30%Tihrvalid
RREADYCLKTovrready30%Tohrready
AWADDR[31:0]CLKTovawaddr30%Tohawaddr
AWBURST[1:0]CLKTovawburst30%Tohawburst
AWCACHE[3:0]CLKTovawcache30%Tohawcache
AWID[3:0]CLKTovawid30%Tohawid
AWLEN[3:0]CLKTovawlen30%Tohawlen
AWLOCK[1:0]CLKTovawlock30%Tohawlock
AWPROT[2:0]CLKTovawprot30%Tohawprot
AWSIZE[2:0]CLKTovawsize30%Tohawsize
AWVALIDCLKTovawvalid30%Tohawvalid
AWREADYCLKTisawready30%Tihawready
WDATA[127:0]CLKTovwdata30%Tohwdata
WID[3:0]CLKTovwid30%Tohwid
WLASTCLKTovwlast30%Tohwlast
WSTRB[15:0]CLKTovwstrb30%Tohwstrb
WVALIDCLKTovwvalid30%Tohwvalid
WREADYCLKTiswready30%Tihwready
BID[3:0]CLKTisbid30%Tihbid
BRESP[1:0]CLKTisbresp30%Tihbresp
BVALIDCLKTisbvalid30%Tihbvalid
BREADYCLKTovbready30%Tohbready

[1] This is a static input to the processor.


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