17.5. L1 and L2 MBIST interfaces

Table 17.5 shows the setup and hold times for the L1 and L2 interfaces

Table 17.5. Timing parameters of the L1 and L2 MBIST interface

SignalClockSetup parameterPercent of clock period Hold parameter
MBISTDATAINL1CLKTismbistdatainl130%Tihmbistdatainl1
MBISTDSHIFTL1CLKTismbistdshiftl130%Tihmbistdshiftl1
MBISTMODEL1CLKTismbistmodel130%Tihmbistmodel1
MBISTRUNL1CLKTismbistrunl130%Tihmbistrunl1
MBISTSHIFTL1CLKTismbistshiftl130%Tihmbistshiftl1
MBISTRESULTL1[2:0]CLKTovmbistresultl130%Tihmbistresultl1
MBISTDATAINL2CLKTismbistdatainl230%Tihmbistdatainl2
MBISTDSHIFTL2CLKTismbistdshiftl230%Tihmbistdshiftl2
MBISTMODEL2CLKTismbistmodel230%Tihmbistmodel2
MBISTRUNL2CLKTismbistrunl230%Tihmbistrunl2
MBISTSHIFTL2CLKTismbistshiftl230%Tihmbistshiftl2
MBISTRESULTL2[2:0]CLKTovmbistresultl230%Tohmbistresultl2
MBISTUSERINL2[18:0]CLKTismbistuserinl230%Tihmbistuserinl2
MBISTUSEROUTL2[4:0]CLKTovmbistuseroutl250%Tohmbistuseroutl2

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