2.4. Jazelle Extension

The Cortex-A8 processor provides a trivial implementation of the Jazelle Extension. This means that the processor does not accelerate the execution of any bytecodes, and all bytecodes are executed by software routines.

In the implementation of the Jazelle Extension:

See the ARM Architecture Reference Manual for information on Jazelle Extension.

The processor provides three registers for the implementation of the Jazelle Extension:

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