17.1. About setup and hold times

The setup and hold times of processor interface signals are necessary timing parameters for analyzing processor performance. This chapter specifies the setup and hold times of the processor interface signals.

The notation for setup and hold times of input signals is:

Tis

Input setup time. Tis is the amount of time the input data is valid before the next rising clock edge.

Tih

Input hold time. Tih is the amount of time the input data is valid after the next rising clock edge.

Figure 17.1 shows the setup and hold times of an input signal.

Figure 17.1. Input timing parameters


The time during which the processor can sample input data is Tissignal.

The notation for setup and hold times of output signals is:

Tov

Output valid time. Tov is the amount of time after the rising clock edge before valid output data appears.

Toh

Output hold time. Toh is the amount of time the output data is valid after the next rising clock edge.

Figure 17.2 shows the setup and hold times of an output signal.

Figure 17.2. Output timing parameters


The timing parameter tables in this chapter show setup and hold parameters of each signal as percentages of the relevant clock as shown in Table 17.1.

Table 17.1. Format of timing parameter tables

SignalClockSetup parameterPercent of clock periodHold parameter
INPUTCLKTisinput50%Tihinput
OUTPUTPCLKTovoutput30%Tohoutput

The setup parameter values are based on the Slow-Slow (SS) corner under the following conditions:

The hold parameter values are based on the Fast-Fast (FF) corner under the following conditions:

The nominal operating voltage for the process is defined to be Vdd.

Note

The hold time requirements for the macrocell I/O are not specified in this document. The hold time is specific to process and implementation requirements and therefore, are controlled by the implementor.

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