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Home > System Control Coprocessor > System control coprocessor registers > c15, L1 data array operations |

The purpose of the L1 data array operations is to:

read the L1 data array contents and write into the system debug data registers

write into the system debug data registers and copy into the L1 data array.

The L1 data array operation is accessible in secure privileged modes only. You can calculate the value of N in Figure 3.75 and Figure 3.76 using the NumSets and LineSize fields as defined in Table 3.42.

Figure 3.75 shows the bit arrangement of the L1 data array read operation.

Figure 3.76 shows the bit arrangement of the L1 data array write operation.

To write one entry in data side L1 data array, for example:

LDR R0, =0x01234567;

MCR p15, 0, R0, c15, c0, 0; Move R0 to D-L1 Data 0 Register

LDR R2, =0x1B;

MCR p15, 0, R2, c15, c0, 1; Move R0 to D-L1 Data 1 Register

LDR R1, =0x800000D8;

MCR p15, 0, R1, c15, c0, 7; Write D-L1 Data 0 or 1 Register to D-L1 data

To read one entry in data side L1 data array, for example:

LDR R1, =0x800000D8;

MCR p15, 0, R1, c15, c2, 7; Read D-L1 data into data L1 Data 0 or 1 Register

MRC p15, 0, R0, c15, c0, 0; Move D-L1 Data 0 Register to R0

MRC p15, 0, R2, c15, c0, 1; Move D-L1 Data 1 Register to R2

To write one entry in instruction side L1 data array, for example:

LDR R0, =0x01234567;

MCR p15, 0, R0, c15, c1, 0; Move R0 to I-L1 Data 0 Register

LDR R2, =0x1B;

MCR p15, 0, R2, c15, c1, 1; Move R0 to I-L1 Data 1 Register

LDR R1, =0x800000D8;

MCR p15, 0, R1, c15, c1, 7; Write I-L1 Data 0 or 1 Register to I-L1 data

To read one entry in instruction side L1 data array, for example:

LDR R1, =0x800000D8;

MCR p15, 0, R1, c15, c3, 7; Read I-L1 data into I-L1 Data 0 or 1 Register

MRC p15, 0, R0, c15, c1, 0; Move I-L1 Data 0 Register to R0

MRC p15, 0, R2, c15, c1, 1; Move I-L1 Data 1 Register to R2

The granularity of the dirty bits is so that two sets of dirty bits are updated for each CP15 L1 DATA array write operation. A doubleword set of dirty bits are updated so that if word 0 or word 1 is being updated, then the D-bit and D-bit parity bits are updated for both word 0 and word 1.