3.2.77. c15, L1 tag array operations

The purpose of the L1 tag array operations is to:

The L1 tag array operation is accessible in secure privileged modes only. You can calculate the value of N in Figure 3.73 and Figure 3.74 using the NumSets and LineSize fields as defined in Table 3.42.

Figure 3.73 shows the bit arrangement of the L1 tag array read operation.

Figure 3.73. L1 tag array read operation format


Figure 3.74 shows the bit arrangement of the L1 tag array write operation.

Figure 3.74. L1 tag array write operation format


To write one entry to the data side L1 tag array, for example:

LDR R0, =0x00500007;            
MCR p15, 0, R0, c15, c0, 0;     Move R0 to D-L1 Data 0 Register
LDR R1, =0x800000C0;            
MCR p15, 0, R1, c15, c0, 6;     Write D-L1 Data 0 Register to D-tag

To read one entry from the data side L1 tag array, for example:

LDR R1, =0x800000C0;            
MCR p15, 0, R1, c15, c2, 6;     Read D-tag into data L1 Data 0 Register
MRC p15, 0, R2, c15, c0, 0;     Move D-L1 Data 0 Register to R2

To write one entry to the instruction side L1 tag array, for example:

LDR R0, =0x00500007;            
MCR p15, 0, R0, c15, c1, 0;     Move R0 to I-L1 Data 0 Register
LDR R1, =0x800000C0;            
MCR p15, 0, R1, c15, c1, 6;     Write I-L1 Data 0 Register to I-tag

To read one entry from the instruction side L1 tag array, for example:

LDR R1, =0x800000C0;            
MCR p15, 0, R1, c15, c3, 6;     Read I-tag into I-L1 Data 0 Register
MRC p15, 0, R2, c15, c1, 0;     Move I-L1 Data 0 Register to R2
Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential