A.3.2. DFT pins and additional MBIST pin requirements during MBIST testing

Table A.4 shows the signals necessary for DFT. It also shows the additional pins required during MBIST testing.

Table A.4. DFT and additional MBIST pin requirements

SignalI/OValue during functional modeValue during MBIST modeDescription

MBISTMODEL1

I01Configures L1 for MBIST mode and disables instruction fetch after reset.

MBISTMODEL2

I01Configures L2 for MBIST mode and disables instruction fetch after reset.
TESTMODEI00Indicates ATPG test mode. Deassert during MBIST mode.
TESTCGATEI01Controls core clock gating during test mode or MBIST mode.
TESTEGATEI00Controls ETM clock gating. Deassert to save power during MBIST mode.
TESTNGATEI00Controls NEON clock gating. Deassert to save power during MBIST mode.
SEI00Scan enable signal. Ensures safe shifting of scan chains.
SAFESHIFTRAMIFI00Prevents the RAM in the instruction fetch unit from performing a write operation during scan shifting.
SAFESHIFTRAMLSI00Prevents the RAM in the load/store unit from performing a write operation during scan shifting.
SAFESHIFTRAML2I00Prevents the RAM in the L2 cache unit from performing a write operation during scan shifting.
SERIALTESTI00Concatenates the wrapper boundary register scan cells into a single scan chain.
SHIFTWRI00IEEE 1500 standard shift signal.
CAPTUREWRI00IEEE 1500 standard capture signal.
WINTESTI00Enables internal testing during ATPG.
WEXTESTI00Enables external testing during ATPG.
WSEI00Wrapper scan enable. Enables serial shifting of the wrapper scan chain.
PRESETnI-0Active-LOW APB reset input.
ACLKENI-1AXI clock enable signal. This signal must be driven HIGH for at least one clock cycle during reset. The value after reset does not affect the MBIST operation.

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