10.3.4. L1 data and L2 cache power domains

During periods when the entire core is not required, you can stop the processor clocks by executing a Wait For Interrupt instruction. However, leakage continues to occur. To remove the leakage component, you must remove the power supplied to the power domains within the processor. However, the time required to remove and restore the power limits the advantage of a full power-down of the processor. A full power-down sequence for the processor might include:

  1. Clean and invalidate the caches, L1 data and L2 caches, to the point of coherency.

  2. Disable the L1 data and L2 cache.

  3. Save off any TLB state such as locked entries, if required.

  4. Save off architectural state.

  5. Reset and power down the processor. See Powering down the integer core power domain.

  6. Power up the processor. See Powering up the integer core and NEON power domains.

  7. Perform a normal software reset sequence.

The largest potential time and energy required in the sequence is the clean and invalidate of the caches. This operation is bounded by the time required to transfer the data into an external memory. To reduce or remove this Clean and Invalidate operation, the processor supports a separate power domain for the L1 data cache in addition to a separate power domain for the L2 cache RAMs. The L1 data cache and L2 unified cache contain hardware reset assistance that is controlled with the input pins L1RSTDISABLE and L2RSTDISABLE, respectively. The L1RSTDISABLE and L2RSTDISABLE pins must be tied LOW to enable hardware reset if the L1 data cache and L2 cache contents are not retained during core power down. Conversely, if the L1 data cache contents and the L2 cache contents are retained by a separate powered-up domain, the L1RSTDISABLE and L2RSTDISABLE pins must be enabled to ensure updated data contained in the caches is not invalidated by the power-up reset sequence. See Hardware RAM array reset for more information about the timing requirements of these pins.

If an implementation places the L1 or L2 cache on separate power domains as shown in Figure 10.13, the rest of the processor can be powered down while the L1 or L2 cache retains their data. This requires that all inputs to the L1 or L2 RAMs such as tag, parity, valid, and data RAMs are clamped to safe values to avoid corrupting the data when entering or exiting a power-down state.

If the L1 data cache contents are placed on a separate power domain, then the L2 cache must also be placed on a separate power domain. The L1 data cache contents cannot be retained without retaining the L2 cache contents. An exception to this rule is the 0KB L2 cache configuration.

Figure 10.13. Retention power domains


Similarly, the L1 data cache can be placed on a separate power domain from the rest of the processor. This L1 data cache power domain can be shared with the L2. However, sharing of the two cache power domains is not required. In addition, all inputs into the L1 data cache RAMs such as tag, HVAB, and data RAMs must be clamped to safe values to avoid corrupting the data when entering or exiting a power-down state.

Note

Data retention within the L1 instruction cache is not supported.

Power cycle the core with L2 cache retaining state

A power down and reset sequence of the processor with the L2 cache retained is as follows:

  1. Clean to the point of unification the L1 data cache.

  2. Save off any TLB state such as locked entries, if required.

  3. Save off architectural state, if required.

  4. Assert L2RSTDISABLE to disable L2 hardware reset.

  5. Reset and power down the processor. See Powering down the integer core power domain.

  6. Power up the processor. See Powering up the integer core and NEON power domains.

  7. Perform a normal software initialization of the L1 instruction and data caches.

  8. Perform a software read of a memory location to determine that the L2 has valid data and to skip the L2 software invalidation.

  9. Before enabling the L2 cache or using any CP15 cache-related operations, software must signal the system to release the L2 cache input clamps and receive confirmation that the clamps have been released.

Power cycle the core with L1 data cache and L2 cache retaining state

A power down and reset sequence of the processor with the L1 data cache and L2 cache is as follows:

  1. Save off any TLB state such as locked entries, if required.

  2. Save off architectural state, if required.

  3. Assert L1RSTDISABLE and L2RSTDISABLE to inhibit hardware reset of the L1 data cache and L2 cache.

  4. Reset and power down the processor. See Powering down the integer core power domain.

  5. Power up the processor. See Powering up the integer core and NEON power domains.

  6. Perform a normal software initialization of the L1 instruction cache.

  7. Perform a software read of a memory location to determine that the L1 data cache and L2 cache have valid data and to skip the software initialization sequence.

  8. Before enabling the L1 data cache or L2 cache, or using any CP15 cache-related operations, software must signal the system to release the L1 data cache and L2 cache input clamps and receive confirmation that the clamps have been released.

Note

The details of how to clamp the inputs to various arrays are implementation-specific and are not described in this document. Care must be taken that nPORESET does not affect the state in the RAM arrays.

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