11.1.4. Pattern selection

The processor implementation includes a toolbox of patterns for testing the arrays. When creating test vectors, you can select the group of algorithms that is most effective for your fabrication process.

Some of the pattern sequence descriptions use the following terms:

R

Read instruction data seed.

W

Write instruction data seed.

R_

Read inverse of instruction data seed.

W_

Write inverse of instruction data seed.

incr

Increment address starting with 0 until address = addrmax.

decr

Decrement address starting with addrmax until address = 0.

wscan

Write entire array.

rscan

Read entire array.

N

Total number of accesses per address location.

Table 11.19 shows the patterns that are selected using the pttn[5:0] field of the MBIST Instruction Register.

Table 11.19. Summary of MBIST patterns

PatternN

Address

updating

Description
CAMBIST--Tests CAM compare logic, see CAMBIST
CKBD4NRow-fastCheckerboard-checkerboard_bar wscan-rscan pattern, see CKBD
COLBAR4NColumn-fastColumn bar-stripe wscan-rscan pattern, see COLBAR
ROWBAR4NRow-fastRow bar-stripe wscan-rscan pattern, see ROWBAR
SOLIDS4NRow-fastSolid wscan-rscan pattern, see SOLIDS
RWXMARCH6NRow-fastStandard R W_ increment-decrement march, see RWXMARCH
RWYMARCH6NColumn-fastStandard R W_ increment-decrement march, see RWYMARCH
RWRXMARCH8NRow-fastStandard R W_ R_ increment-decrement march, see RWRXMARCH
RWRYMARCH8NColumn-fastStandard R W_ R_ increment-decrement march, see RWRYMARCH
XMARCHC14NRow-fast

Standard marchC, see XMARCHC

R W_ R_ incr, R_ W R_ incr, R W_ R_ decr R_ W R_decr

YMARCHC14NColumn-fast

Standard marchC, see YMARCHC

R W_ R_ incr, R_ W R_ incr, R W_ R_ decr R_ W R_decr

XADDRBAR4NRow-fastWscan/rscan through opposite addresses, see XADDRBAR
YADDRBAR4NColumn-fastWscan/rscan through opposite addresses, see YADDRBAR
WRITEBANG20NRow-fastCustom bitline stress test, see WRITEBANG W_ R_ (wsac 5) R_ W
READBANG17NRow-fastCustom bitcell read stress test, see READBANG
FAIL6NRow-fastR W march with built-in failures, see FAIL
ADDRDECODERN(1 + 2log2N)NADetection of open decoder faults on address lines, see ADDRESS DECODER
Default GO-NOGO32NMixCKBD-RWRYMARCH-WRITEBANG, see GO-NOGO

WCKBD

WCOLBAR

WROWBAR

WSOLIDS

1N-Single pass wscan for IDDQ and data retention style tests

RCKBD

RCOLBAR

RROWBAR

RSOLIDS

1N-Single pass rscan for IDDQ and data retention style tests

CAMBIST

The CAMBIST performs a simultaneous match check across all 32 entries by comparing each entry against an incoming compare value. This function is executed by performing a bitwise XOR of the inverted compare value and each individual CAM entry. If the XOR is true, a hit is determined. CAMBIST tests this compare function by testing that each CAM bit is capable of generating a hit and a miss for both 1 and 0.

CAMBIST performs the following sequence:

  1. Write all entries with 0xA.

  2. Write 0s to entry 0.

  3. Compare 0s and check for hit with 0s.

  4. Compare 0x00000001 and check for miss.

  5. Write 0x00000001 into CAM entry.

  6. Check for hit and miss with compare = 0x00000001 and 0s.

  7. Left shift compare bit until every bit is checked for hit and miss, repeating steps 4-6 until all bits are tested.

  8. Write 0xAs to tested entry.

  9. Repeat steps 2-8 for all 32 CAM entries.

Note

Normal MBIST tests CAM array entries. The CAMBIST routine checks the compare and hit functions only.

CKBD

CKBD is a row-fast checkerboard scan pattern in which the following condition determines data seed inversion:

invert = row_index[0] ^ col_index[0]

CKBD performs the following sequence:

  1. wscan array, data_seed = true.

  2. rscan array, data_seed = true.

  3. wscan array, data_seed = invert.

  4. rscan array, data_seed = invert.

Figure 11.13 shows the physical array after the first CKBD pass.

Figure 11.13. Physical array after pass 1 of CKBD


COLBAR

COLBAR is a column-fast stripe scan pattern in which the following condition determines data seed inversion:

invert = col_index[0]

COLBAR performs the following sequence:

  1. wscan array, data_seed = true.

  2. rscan array, data_seed = true.

  3. wscan array, data_seed = invert.

  4. rscan array, data_seed = invert.

Figure 11.14 shows the physical array after the first COLBAR pass.

Figure 11.14. Physical array after pass 1 of COLBAR


ROWBAR

ROWBAR is a row-fast bar-stripe scan pattern in which the following condition determines data seed inversion:

invert = row_index[0]

ROWBAR performs the following sequence:

  1. wscan array, data_seed = true.

  2. rscan array, data_seed = true.

  3. wscan array, data_seed = invert.

  4. rscan array, data_seed = invert.

Figure 11.15 shows the physical array after the first ROWBAR pass.

Figure 11.15. Physical array after pass 1 of ROWBAR


SOLIDS

SOLIDS is a row-fast scan pattern in which data seed inversion is not a function of address.

SOLIDS performs the following sequence:

  1. wscan array, data_seed = true.

  2. rscan array, data_seed = true.

  3. wscan array, data_seed = invert.

  4. rscan array, data_seed = invert.

RWXMARCH

RWXMARCH is a row-fast RW increment/decrement march. It performs the following sequence:

  1. wscan data to entire array.

  2. R, W_, incr.

  3. R_, W, decr.

  4. rscan data from entire array.

Figure 11.16 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.16. Row 1 column 2 state during pass 2 of RWXMARCH


RWYMARCH

RWYMARCH is a column-fast RW increment/decrement march. It performs the following sequence:

  1. wscan data to entire array.

  2. R, W_, incr.

  3. R_, W, decr.

  4. rscan data from entire array.

Figure 11.17 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.17. Row 1 column 2 state during pass 2 of RWYMARCH


RWRXMARCH

RWRXMARCH is a row-fast RWR increment/decrement march. It differs from the RW march in that it requires consecutive reads of opposite data from consecutive addresses.

RWRXMARCH performs the following sequence:

  1. wscan data to entire array.

  2. R, W_, R_, incr.

  3. R_, W, R, decr.

  4. rscan data from entire array.

Figure 11.18 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.18. Row 1 column 2 state during pass 2 of RWRXMARCH


RWRYMARCH

RWRYMARCH is a column-fast RWR increment/decrement march. It performs the following sequence:

  1. wscan data to entire array.

  2. R, W_, R_, incr.

  3. R_, W, R, decr.

  4. rscan data from entire array.

Figure 11.19 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.19. Row 1 column 2 state during pass 2 of RWRYMARCH


XMARCHC

XMARCHC is a row-fast RWR increment/decrement march for embedded memory test. It differs from the MARCH patterns in that it repeats the increment/decrement passes with the opposite start data.

XMARCHC performs the following sequence:

  1. wscan data.

  2. R, W_, R_, incr.

  3. R_, W, R, incr.

  4. R, W_, R_, decr.

  5. R_, W, R, decr.

  6. rscan data, decr.

Figure 11.20 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.20. Row 1 column 2 state during pass 2 of XMARCHC


YMARCHC

YMARCHC is a column-fast MARCHC. It performs the following sequence:

  1. R, W_, R_, incr.

  2. R, W_, R_, incr.

  3. R_, W, R, incr.

  4. R, W_, R_, decr.

  5. R_, W, R, decr.

  6. rscan data, decr.

Figure 11.21 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.21. Row 1 column 2 state during pass 2 of YMARCHC


XADDRBAR

XADDRBAR is a write/read row-fast scan pattern with two exceptions. This algorithm uses only half of the MBIST address space. For each address, XADDRBAR also makes an access to the inverted address with inverted data. Unlike the standard scan pattern that moves through the entire address space linearly, it alternates between opposite addresses until it addresses the entire array.

XADDRBAR performs the following sequence:

  1. W to Addr, W_ to inverse of Addr, incr until AddrMax/2.

  2. R from Addr, R_ from inverse of Addr, increment until AddrMax/2.

  3. W_ to Addr, W to inverse of Addr, decrement from AddrMax/2 to zero.

  4. R_ from Addr, R from inverse of Addr, decrement from AddrMax/2 to zero.

In a 4 4 array, Figure 11.22 shows:

  • the order of array accesses during XADDRBAR execution

  • the data after pass 1 of XADDRBAR using a data seed of 0.

Figure 11.22. XADDRBAR array accessing and data


YADDRBAR

The YADDRBAR pattern is similar to the XADDRBAR pattern with the exception of incrementing and decrementing the array column-fast.

In a 4 4 array, Figure 11.23 shows:

  • the order of array accesses during YADDRBAR execution

  • the data after pass 1 of YADDRBAR using a data seed of 0.

Figure 11.23. YADDRBAR array accessing and data


WRITEBANG

WRITEBANG is a row-fast bitline stress pattern. It operates on a bitline pair, that is, a column. It tries to create slow reads from target data cells in the column that can cause hard faults in self-timed and high-speed RAMs. It writes the bitline multiple times to the opposite data state of the target read, trying to create an imbalance in the bitline pair that the cell must correct. The pattern reveals insufficient bitline precharge or equalization. The target cell has opposite data from all other cells on the bitline pair. This is a worst-case bitline condition for a cell to drive because any leakage from other cells in the column oppose the targeted read. In the following description, wsac indicates a write to row 0, a sacrificial (untested) row used during test. WRITEBANG performs the following sequence:

  1. Wscan data to entire array.

  2. W_, R_, wsac, wsac, wsac, wsac, wsac, R_, W, incr.

  3. Wscan databar.

  4. W, R, wsac_, wsac_, wsac_, wsac_, wsac_, R, W_, incr.

Figure 11.24 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.24. WRITEBANG


READBANG

READBANG is a row-fast bitcell stress test pattern. The pattern operates on a bitcell, reading it multiple times in an attempt to weaken its latched margin. It writes opposite data to the sacrificial row, and makes a final read of the target cell. In the following description, wsac indicates a write to row 0, a sacrificial row used during test. READBANG performs the following sequence:

  1. Wscan data to entire array.

  2. R, R, R, R, R, wsac_, R, W_, incr.

  3. R_, R_, R_, R_, R_, wsac, R_, W, incr.

Figure 11.25 shows the state of row 1, column 2 in a 4 4 array during pass 2.

Figure 11.25. READBANG


FAIL

FAIL is a row-fast algorithm similar to the RWXMARCH pattern but contains injected failures of opposite data written during the wscan portion of the algorithm in one of every 16 accesses. Running FAIL with the production test suite ensures that the MBIST error detection and reporting occurs properly. You can use FAIL to check bitmap mode function in simulation.

ADDRESS DECODER

ADDRESS DECODER targets the address decoders in memory instead of the bitcells. It performs the following sequence:

  1. W addr.

  2. W_ (Addr ^ shift_reg).

  3. R Addr, shift_reg << 1.

  4. Repeat steps 2 and 3 until shift_reg = Addr MSB.

  5. Incr addr, repeat steps 1-4 until addr expire.

The shift register is a one-hot register with a width equal to the number of address bits.

The test time for the maximum L2 indexing (17 bits) is:

(1 + (2 17)) 217 = 4,587,520 cycles, not including latency.

The test time for the maximum L1 indexing (11 bits) is:

(1 + (2 11)) 211 = 47,104 cycles, not including latency.

GO-NOGO

GO-NOGO is a concatenation of other basic patterns. You can choose between a standard default GO-NOGO sequence and a programmable sequence. The default GO-NOGO performs the following sequence:

  1. CKBD, data seed = 0x5.

  2. RWRYMARCH, data seed = 0xF.

  3. WRITEBANG, data seed = 0xC.

You can select up to eight different pattern combinations and select the data seed of your choice.

Note

Be sure to properly order the sequence of tests. For example, a write CKBD followed by a read solid always fails because the data read was different from what was written.

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