10.3.3. Debugging the processor while powered down

If the processor is powered down, the SoC can still be functional and used for debug across the power domains. If the debugger accesses the processor, the debug PCLK, ETM CLK, and ETM ATCLK domains must be powered up. See Chapter 12 Debug for more information on debugging during power down.

If the integer core power domain is powered down while the debug PCLK, ETM CLK, and ETM ATCLK power domains are still powered up, all inputs from the integer core power domain to the debug PCLK, ETM CLK, and ETM ATCLK power domains must be clamped to benign values.

Powering down the integer core power domain

Apply the following sequence to power down the integer core power domain:

  1. Assert DBGPWRDWNREQ to indicate that processor debug and ETM resources are not available for APB accesses. Wait for DBGPWRDWNACK to be asserted.

    Note

    The ETMPWRDWNREQ and ETMPWRDWNACK signals are not required because debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.

  2. Assert ARESETn, ARESETNEONn, and nPORESET. You must assert ARESETn, ARESETNEONn, and nPORESET for at least eight CLK cycles before activating the integer core and NEON clamps.

  3. Activate the NEON output clamps and the clamps to the debug PCLK, ETM CLK, and ETM ATCLK power domains from the core by asserting the CLAMPCOREOUT and CLAMPNEONOUT inputs HIGH.

  4. Remove power from the integer core and NEON power domains while retaining power to the debug PCLK, ETM CLK, and ETM ATCLK power domains.

Powering up the integer core and NEON power domains

Apply the following sequence to power up the integer core and NEON power domains:

  1. Apply power to the integer core and NEON power domains while keeping ARESETn, ARESETNEONn and nPORESET asserted.

  2. Release the NEON output clamps and the clamps to the debug PCLK, ETM CLK, and ETM ATCLK power domains from the core by deasserting CLAMPCOREOUT and CLAMPNEONOUT.

  3. Deassert DBGPWRDWNREQ to indicate that processor debug and ETM resources are available. There is no requirement for hardware to wait for DBGPWRDWNACK to be deasserted.

    Note

    The ETMPWRDWNREQ and ETMPWRDWNACK signals are not required because debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.

  4. Continue a normal power-on reset sequence.

Powering up the integer core power domain while keeping NEON powered down

Apply the following sequence to power up the integer core while keeping NEON powered down:

  1. Apply power to the integer core power domain while keeping ARESETn, ARESETNEONn and nPORESET asserted. Be sure to keep the NEON power domain off.

  2. Release the clamps to the debug PCLK, ETM CLK, and ETM ATCLK power domains from the core by deasserting CLAMPCOREOUT and keeping CLAMPNEONOUT asserted.

  3. Deassert DBGPWRDWNREQ to indicate that processor debug and ETM resources are available. There is no requirement for hardware to wait for DBGPWRDWNACK to be deasserted.

    Note

    The ETMPWRDWNREQ and ETMPWRDWNACK signals are not required because debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.

  4. Continue a normal power-on reset sequence while ARESETNEONn and CLAMPNEONOUT remain asserted. To power up the NEON power domain, see Powering up the NEON power domain while the processor is not in reset.

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