11.1.2. MBIST registers

Table 11.1 shows the MBIST registers. See Figure 11.7 for information about the timing of an MBIST instruction load.

Table 11.1. MBIST register summary

RegisterAccessReference
L1 MBIST Instruction RegisterWSee L1 MBIST Instruction Register
L2 MBIST Instruction RegisterWSee L2 MBIST Instruction Register
L1 and L2 MBIST GO-NOGO Instruction RegistersWSee L1 and L2 MBIST GO-NOGO Instruction Registers
L1 MBIST Datalog RegisterRSee L1 MBIST Datalog Register
L2 MBIST Datalog RegisterRSee L2 MBIST Datalog Register

L1 MBIST Instruction Register

Figure 11.1 shows the fields of the L1 MBIST Instruction Register.

Figure 11.1. L1 MBIST Instruction Register bit assignments


pttn[5:0]

Use the pttn[5:0] field to select test patterns as Table 11.2 shows.

Table 11.2. Selecting a test pattern with pttn[5:0]

FieldSelected test pattern
pttn[5:0]Pattern select field:[1]
 

b010010 = PTTN_WRITE_SOLID

b010011 = PTTN_READ_SOLID

b100001 = PTTN_SOLIDS

b000010 = PTTN_WRITE_CKBD

b000011 = PTTN_READ_CKBD

b100011 = PTTN_CKBD

b000100 = PTTN_XMARCH_C

b000101 = PTTN_PTTN_FAIL

b000110 = PTTN_RW_XMARCH

b000111 = PTTN_RW_YMARCH

b001000 = PTTN_RWR_XMARCH

b001001 = PTTN_RWR_YMARCH

b001010 = PTTN_WRITEBANG

b101010 = PTTN_READBANG

b001011 = PTTN_YMARCH_C

b001100 = PTTN_WRITE_ROWBAR

b001101 = PTTN_READ_ROWBAR

b101101 = PTTN_ROWBAR

b001110 = PTTN_WRITE_COLBAR

b001111 = PTTN_READ_COLBAR

b101111 = PTTN_COLBAR

b010000 = PTTN_RW_XADDRBAR

b010001 = PTTN_RW_YADDRBAR

b010100 = PTTN_ADDR_DEC

b000000 = PTTN_GONOGO[2]

b111111 = PTTN_SLAVE

[2] Default value of pttn[5:0].


Note

The PTTN_SLAVE pattern (b111111) is for testing only the I-CAMBIST and D-CAMBIST.

rtfail

Setting the rtfail bit to 1 enables the fail signal to assert on every cycle that a failure occurs. Clearing the rtfail bit to 0 causes a sticky failure reporting, and the fail signal remains asserted after the first failure that occurs. Reset clears the rtfail bit to 0.

bitmap

Setting the bitmap bit to1 enables bitmap test mode. Reset clears the instruction register bitmap bit to 0. See Bitmap test mode.

dseed[3:0]

Write the data seed in the dseed field. The MBIST controller repeats the dseed data to the full array bus width. The reset value of dseed[3:0] is b0000.

L1_array_sel[22:0]

Set bits in the L1_array_sel[22:0] field to select the L1 arrays for test. The MBIST executes the selected arrays serially beginning with the array indicated by the LSB. Table 11.3 shows how each bit selects one of the L1 arrays. The reset value of the L1_array_sel is 23'h1FFFFF.

Table 11.3. Selecting the L1 arrays to test with L1_array_sel[22:0]

Bit Array selected
[0]I-RAM word0 [31:0] parity and dirty included.a
[1]I-RAM word1 [63:32] parity and dirty included.a
[2]I-RAM word2 [95:64] parity and dirty included.a
[3]I-RAM word3 [127:96] parity and dirty included.a
[4]I-CAM array.
[5]I-PA.
[6]I-tag.
[7]I-attributes of TLB.
[8]I-HVAB.
[9]BTBI.[1]
[10]BTBH.a
[11]GHB.
[12]D-RAM word0 [31:0] parity and dirty included.a
[13]D-RAM word1 [63:32] parity and dirty included.a
[14]D-RAM word2 [95:64] parity and dirty included.a
[15]D-RAM word3 [127:96] parity and dirty included.a
[16]D-CAM array.
[17]D-PA.
[18]D-tag.
[19]D-attributes of TLB.
[20]D-HVAB.
[21]I-CAMBIST. Tests CAM compare logic.
[22]D-CAMBIST. Tests CAM compare logic.

[1] You can test the RAM and BTB arrays by accessing the entire array width during writes. The selected words are compared according to the L1_array_sel bit currently under test. For this reason, exercise care when creating iddq or data retention patterns because individual word slices cannot be initialized and maintained with different data seeds.


Note

Do not test the CAMBIST arrays in the same run as other arrays.

L1_config[14:0]

The L1_config[14:0] field contains five 3-bit fields for defining the number of physical rows in each L1 array as Table 11.4 shows.

Table 11.4. L1_config[14:0]

L1_config bit fieldField name
L1_config[14:12]HVAB_rows[2:0]
L1_config[11:9]GHB_rows[2:0]
L1_config[8:6]BTB_rows[2:0]
L1_config[5:3]TAG_rows[2:0]
L1_config[2:0]DATA_rows[2:0]

The value in each field is implementation-defined and programmable to ensure that physically targeted RAM tests perform correctly.

Note

Only arrays with variable row sizes are programmable. The CAM, PA, and attributes arrays have an architecturally fixed depth of 32. Because of timing limits, physical rows beyond 512 are not supported.

Table 11.5 shows the possible values for each of the 4-bit fields of L1_config[14:0].

Table 11.5. Configuring the number of L1 array rows with L1_config[14:0]

Field valueNumber of rows sharing a bitline pair
b00016
b00132
b01064
b011128
b100256
b101512
b110-b111Reserved

Reset clears the HVAB_rows[2:0], GHB_rows[2:0], and TAG_rows[2:0] fields to b000. Reset initializes the BTB_rows[2:0] and DATA_rows[2:0] fields to b010.

L1_ADDR_SCRAMBLE[183:0]

Proper physical mapping prevents unintended pattern sequences that result in loss of test quality. This field defines the physical-to-logical address scramble settings for your implementation. See the Cortex-A8 Release Notes for information on how to program this for your design.

L2 MBIST Instruction Register

Figure 11.2 shows the fields of the L2 MBIST Instruction Register.

Figure 11.2. L2 MBIST Instruction Register bit assignments


The pttn[5:0], rtfail, bitmap, and dseed[3:0] fields function the same as in the L1 MBIST Instruction Register.

L2_ram_sel[4:0]

Set bits in the L2_ram_sel[4:0] field to select the L2 RAMs for test as Table 11.6 shows.

Table 11.6. Selecting L2 RAMs for test with L2_ram_sel[4:0]

BitSelected RAM
[0]L2 data RAM low order bits [64:0]
[1]L2 data RAM high order bits [129:65]
[2]L2 parity RAM
[3]L2 tag RAM
[4]L2 valid RAM

Setting an L2_ram_sel bit selects the corresponding RAM for test.

The MBIST accesses the RAMs serially in the order shown in Table 11.6, except that the L2 tag RAM and L2 valid RAM are tested in parallel. You can set the L2ValSer bit to 1 to test these two RAMs serially. See L2ValSer.

The reset value of the L2_ram_sel[4:0] field is b11111.

L2_config[22:0]

The L2_config[22:0] field contains fields for selecting:

  • read and write latency of the L2 data array

  • read and write latency of the L2 tag array

  • number of rows of the L2 data, parity, tag and valid physical RAM

  • testing of valid RAM separately or in parallel with tag RAM testing

  • column address LSB sequencing of 00, 01, 10, 11 or 00, 01, 11, 10.

Table 11.7 shows the bit fields of L2_config[22:0].

Table 11.7. L2_config[22:0]

L2_config bit fieldField name
L2_config[22:19]L2DLat[3:0]
L2_config[18:17]L2TLat[1:0]
L2_config[16:5]L2Rows[11:0]
L2_config[4]L2ValSer
L2_config[3:0]L2AdLSB[3:0]

L2DLat[3:0]

Use the L2DLat[3:0] field to select the read and write latency of the L2 data array as Table 11.8 shows. The reset value of the L2DLat[3:0] field is b1111.

Table 11.8. Selecting L2 data array latency with L2DLat[3:0]

L2DLat[3:0]Wait states
b00002
b00012
b00103
b00114
b01005
b01016
b01107
b01118
b10009
b100110
b101011
b101112
b110013
b110114
b111015
b111116

L2TLat[1:0]

Use the L2TLat[1:0] field to select the read and write latency of the L2 tag array as Table 11.9 shows. Reset sets the L2TLat[1:0] field, selecting four wait states.

Table 11.9. Selecting L2 tag array latency with L2TLat[1:0]

L2TLat[1:0]Wait states
b002
b012
b103
b114

L2Rows[11:0]

The four 3-bit fields in the L2Rows[11:0] field control the number of rows in the data, parity, tag, and valid RAMs. Table 11.10 shows the fields that control each of the four RAMs.

Table 11.10. Selecting the L2 RAMs with L2Rows[11:0]

Bit rangeReset valueFunction
[11:9]b100Selects number of data RAM rows
[8:6]b100Selects number of parity RAM rows
[5:3]b000Selects number of tag RAM rows
[2:0]b000Selects number of valid RAM rows

Table 11.11 shows how to configure array depth with the L2Rows fields.

Table 11.11. Configuring the number of L2 RAM rows with L2Rows[11:0]

Field valueNumber of rows sharing a bitline pair
b00016
b00132
b01064
b011128
b100256
b101512
b110-b111Reserved

Not all row settings are valid for all RAMs in all L2 cache size configurations. Table 11.12 shows the range of values from Table 11.11, that is possible for each RAM type, and for each cache size.

Table 11.12. Valid L2 array row numbers

 Data/parity RAM (rows) Tag/valid RAM (rows)

Cache size (KB)

Valid range
12832-51216-128
25632-51216-128
51232-51216-128
102464-51216-256

L2ValSer

By default, the MBIST tests the L2 tag RAM and L2 valid RAM at the same time. Table 11.13 shows that you can select serial testing of the tag and valid RAMs by setting the L2ValSer bit to 1. The reset value of the L2ValSer bit is 0.

When L2ValSer is 0, that is, parallel testing is selected, the address scramble configuration for the valid RAM is the same as that of the tag RAM. This means that the valid RAM uses the tag RAM address scramble configuration, even if the tag RAM is not selected for test. The L2ValSer bit is provided to enable you to serially test the tag RAM with different address scramble configurations.

Table 11.13. Selecting the L2ValSer test type

L2ValSerTesting of L2 tag RAM and L2 valid RAM
1Serial testing
0Parallel testing

L2AdLSB[3:0]

Use the L2AdLSB[3:0] field to select how to increment or decrement the two LSBs of the column address of L2 valid, tag, parity and data RAM accesses. This field is provided as a way to configure non-linear address sequences found in some compiled RAMs. Table 11.14 shows the L2 array controlled by each L2AdLSB[3:0] bit.

Table 11.14. Selecting L2 RAMs for LSB control

L2AdLSB[3:0] bitSelected RAM
[0]L2 valid RAM
[1]L2 tag RAM
[2]L2 parity RAM
[3]L2 data RAM

Table 11.15 shows how each L2AdLSB[3:0] bit controls the increment and decrement sequence of the two column address LSBs.

Table 11.15. Selecting counting sequence of L2 RAM column address LSBs

L2AdLSB[n]LSB increment sequenceLSB decrement sequence
[0]00, 01, 10, 1111, 10, 01, 00
[1]00, 01, 11, 1010, 11, 01, 00

The reset value of the L2AdLSB[3:0] field is b0000.

L2_ADDR_SCRAMBLE[289:0]

Proper physical mapping prevents unintended pattern sequences that result in loss of test quality. Use the ADDR_SCRAMBLE[289:0] field to define the physical-to-logical address scramble setting for your implementation. See the Cortex-A8 Release Notes for information on how to program this for your design.

L1 and L2 MBIST GO-NOGO Instruction Registers

You can use the L1 and L2 MBIST GO-NOGO Instruction Registers to program a custom sequence of up to eight patterns for either L1 or L2 memory. Figure 11.3 shows the fields of the L1 and L2 MBIST GO-NOGO Instruction Registers.

Note

GO-NOGO describes the default GO-NOGO sequence available at power-up.

Figure 11.3. L1 and L2 MBIST GO-NOGO Instruction Registers bit assignments


Each GNG[10:0] field is a concatenation of three fields as Table 11.16 shows.

Table 11.16. GNG[10:0] field

GNG[10:0] bit fieldField name
GNG[10]Valid
GNG[9:6]data seed[3:0]
GNG[5:0]pattern selection[5:0]

The patterns execute in order, starting with GNG1. It is not necessary to load the entire register when fewer than eight patterns are required. If you load fewer than eight patterns, the unloaded fields cannot execute because their valid bits are cleared to 0 at reset.

For example, to execute a READBANG with a data seed of 0x6 followed by a COLBAR with a data seed of 0xF, you only have to load two fields:

1_0110_101010 → 1_1111_10111 =  GNG1[10:0] →  GNG2[10:0]

See READBANG and COLBAR for more details.

Figure 11.4 shows the L1 MBIST GO-NOGO Instruction Register contents after loading a COLBAR with a data seed of 0xF and a READBANG with a data seed of 0x6.

Figure 11.4. L1 MBIST GO-NOGO Instruction Register example with two patterns


The MBISTSHIFTL1 signal must toggle one cycle before initiation and one cycle before completion of the MBISTDATAINL1 stream as Figure 11.7 shows. During GO-NOGO instruction load, MBISTDSHIFTL1 must toggle at the same time as MBISTSHIFTL1. See Figure 11.8.

L1 MBIST Datalog Register

The L1 MBIST Datalog Register records information about failing arrays. Figure 11.5 shows the fields of the L1 MBIST Datalog Register.

Figure 11.5. L1 MBIST Datalog Register bit assignments


ArrayFail[22:0]

Read the ArrayFail[22:0] field to identify arrays that produce failures. The bits in this field correspond to the bits in the L1_array_sel[22:0] field in the L1 MBIST Instruction Register. Table 11.5 shows how each bit corresponds to one of the L1 arrays. Testing more than one array while not in bitmap test mode can set more than one ArrayFail[22:0] bit to 1. The least-significant 1 in the ArrayFail[22:0] field indicates the first failing array.

expect_data[3:0]

Read the expect_data[3:0] field for the expected data seed for the first failing array. Because data seed toggling occurs throughout pattern execution, the value in this field does not always correspond to the programmed data seed.

fail_addr[16:2]

Read the fail_addr[16:2] field for the physical address of the first failing array. See the address scramble information contained within the Design for Test implementation documentation for details on shows how this address is constructed.

failing_bits[37:0]

Read the failing_bits[37:0] field to identify failing bits in the first array that fails. This field contains the EXCLUSIVE-OR of read data and expect data.

alg_pass[3:0]

For the first failing array, read the alg_pass[3:0] field to identify which pass of the algorithm produced a failure. For example, the CKBD algorithm has four passes, wscan, rscan, wscan, and rscan, numbered 1, 2, 3, and 4. Because failures only occur on reads, a CKBD failure results in an alg_pass[3:0] value of b0010 or b0100.

pattern[5:0]

Read the pattern[5:0] field to identify the pattern running at the time of the first failure. Table 11.2 shows the pattern codes. This field is useful when running more than one pattern during a GO-NOGO test.

L2 MBIST Datalog Register

Figure 11.6 shows the fields of the L2 MBIST Datalog Register.

Figure 11.6. L2 MBIST Datalog Register bit assignments


failing_ram[4:0]

Read the failing_ram[4:0] field to identify the RAMs that produce failures. The bits in this field correspond to the bits in the L2_ram_sel[4:0] field in the L2 MBIST Instruction Register. Table 11.6 shows how each bit corresponds to one of the L2 RAMs. Testing more than one RAM while not in bitmap test mode can set more than one failing_ram[4:0] bit to 1. The least-significant bit that is set to 1 in the failing_ram[4:0] field indicates the first failing RAM.

Note

When the L2ValSer bit is 0, the tag RAM and valid RAM are tested in parallel. When testing both these RAM in parallel, a failure in either RAM sets both bit [3] and bit [4] in the failing_ram[4:0] field to 1. To determine if the tag RAM, valid RAM, or both failed, process the failing_bits[32:0] field, see Table 11.18.

expect_data[3:0]

Read the expect_data[3:0] field for the expected data seed for the first failing RAM. Because data seed toggling occurs throughout algorithm execution, the value in this field does not always correspond to the programmed data seed.

fail_addr[16:0]

Read the fail_addr[16:0] field for the physical address of the first RAM failure. This is the address sent to the RAM through the L2 MBIST interface. See the Cortex-A8 Release Notes for information on how you can construct this address.

When testing the data array, there are no cache way select bits, but the index value is still right-justified with fail_addr[0]. You can ignore the upper bits of this field that might be unused for smaller cache sizes (except for bit [16], which is always zero). The values shifted out of unused address bits reflect the values assigned to those bits in the address scramble configuration.

When testing the tag array, bits [16:15] of this field contain the cache way select bits, and the tag array index value is the least-significant bits of fail_addr. Because the fail_addr[14:11] bits are not used for the tag array, they are always zero. Similar to the data array, the upper bits of the array index value are not used for lower cache sizes and can be ignored. Values to these upper bits are supplied by the address scramble configuration.

Table 11.17 shows how the cache ways are grouped into two ways of read data sent back from the tag RAMs.

Table 11.17. L2 cache way grouping

Test sequence number[1]Cache way grouping in read data
0way 1, way 0
1way 3, way 2
2way 5, way 4
3way 7, way 6

[1] Test sequence number is the order that the MBIST controller accesses the cache ways.


The lower-numbered cache ways are always assigned to bits [22:0] of the read data bus for the current test group. The valid RAM contains two data bits for each of the eight cache ways for a total of 16 bits. To achieve a high test quality, all 16 bits are tested in parallel when testing the first group of cache ways. Because the valid bits are typically implemented as a single 16-bit RAM, testing all cache ways in parallel enables the full 16 bits to be accessed each time instead of testing it in slices. This provides greater flexibility with data backgrounds and can reduce test time if the valid RAM is tested serially after the tag RAM.

When testing tag RAMs and valid RAMs in parallel, the valid RAM chip select is disabled to prevent the valid RAM from being accessed during testing of subsequent groups of cache ways within the tag array.

read_mux

The read_mux bit indicates which half of the 65-bit read produced the first failure:

0

Indicates failure in bits [31:0].

1

Indicates failure in bits [64:32].

failing_bits[32:0]

Read the failing_bits[32:0] field to identify failing bits in the first RAM that fails. This field contains the EXCLUSIVE-OR of read data and expect data. Table 11.18 shows how to identify failing L2 bits.

Table 11.18. Identifying failing L2 bits with failing_bits[32:0]

failing_ram[4:0]read_muxfailing_bits[32:0] 
  Valid bits[1]Value
Data, low order0[31:0]Data RAM bits [31:0]
Data, low order1[32:0]Data RAM bits [64:32]
Data, high order0[31:0] Data RAM bits [96:65]
Data, high order1[32:0]Data RAM bits [129:97]
Parity0[2][15:0] Parity RAM bits [15:0]
Tag/valid RAMs0[31:0] Tag RAM read bits [15:0][3], valid RAM read bits [15:0]
Tag/valid RAMs1[29:0] Tag RAM read bits [45:16]b

[1] Unused bits are RAZ.

[2] The read_mux value for the parity RAM is always 0 because it is only 16 bit-wide and is always stored in the lower half of the 65-bit read bus.

[3] Not all tag RAM read bits are active. The MBIST controller masks any unused bits and does not generate a failure.


alg_pass[3:0]

Read the alg_pass[3:0] field to identify which pass of the algorithm produced a failure in the first failing RAM. A pass is defined as one complete pass through the entire address space of the RAM under test. The numbering starts with b0001, indicating the first pass.

pattern[5:0]

Read the pattern[5:0] field to identify the pattern running at the time of the first failure. Table 11.2 shows the pattern codes. This field is useful in GO-NOGO testing when more than one pattern is run during the test.

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