A.6. Miscellaneous signals

Miscellaneous signalsTable A.7 shows the signals not included in the previous tables.

Table A.7. Miscellaneous signals

SignalI/OResetDescription
nPORESETI-

Active-LOW power-on reset input:

0 = apply power-on reset

1 = do not apply power-on reset.

ARESETnI-

Active-LOW AXI reset input:

0 = apply AXI reset

1 = do not apply AXI reset.

ARESETNEONnI-

Active-LOW NEON reset input:

0 = apply NEON reset

1 = do not apply NEON reset.

SECMONOUTENI-

Security monitor output enable:

0 = disables SECMONOUT[86:0]

1 = enables SECMONOUT[86:0].

This pin is only sampled during reset of the processor.

L1RSTDISABLE

I

-

L1 hardware reset disable input:

0 = the L1 valid RAM contents are reset by hardware

1 = the L1 valid RAM contents are not reset by hardware.

L2RSTDISABLEI

-

L2 hardware reset disable input:

0 = the L2 valid RAM contents are reset by hardware

1 = the L2 valid RAM contents are not reset by hardware.

CLKSTOPREQI-

Clock stop request:

0 = do not stop the internal clocks

1 = cause the processor to stop the internal clocks and to assert the CLKSTOPACK output.

CLKSTOPACKO0

Clock stop acknowledge:

0 = the internal clocks are not stopped

1 = the internal clocks are stopped.

SECMONOUT[86:0]OUndefined

Security monitor output:

[19:0] = pipeline 0 instruction address bits[31:12]

[39:20] = pipeline 1 instruction address bits[31:12]

[59:40] = L1 data address bits[31:12]

[64:60] = exception encoding

[69:65] = CPSR[4:0] = mode bits, M[4:0]

[73:70] = CPSR[8:5] = bits A, I, F, and T

[74] = CPSR[24] = J bit

[75] = CP15 Secure Configuration Register bit[0], NS

[76] = CP15 Secure Control Register bit[0], M

[77] = CP15 Secure Control Register bit[2], C

[78] = CP15 Secure Control Register bit[12], I

[79] = IMB instruction executed flag

[80] = DMB or DWB instruction executed flag

[81] = pipeline 0 instruction address valid flag

[82] = pipeline 1 instruction address valid flag

[83] = condition code fail pipeline 0 valid flag

[84] = condition code fail pipeline 1 valid flag

[85] = exception valid flag

[86] = L1 data address valid flag.

STANDBYWFIOb0

Standby mode flag generated by WFI operation:

0 = processor not in standby mode

1 = processor in standby mode.

nFIQI-

Active-LOW asynchronous fast interrupt request:

0 = activate fast interrupt

1 = do not activate fast interrupt.

The processor treats the nFIQ input as level sensitive. The nFIQ input must be asserted until the processor acknowledges the interrupt.

nIRQI-

Active-LOW asynchronous interrupt request:

0 = activate interrupt

1 = do not activate interrupt.

The processor treats the nIRQ input as level sensitive. The nIRQ input must be asserted until the processor acknowledges the interrupt.

VINITHII-

Controls the location of the exception vectors at reset:

0 = starts exception vectors at address 0x00000000

1 = starts exception vectors at address 0xFFFF0000.

This pin is only sampled during reset of the processor.

CFGTEI-

Controls the state of TE bit in the CP15 c1 Control Register at reset:

0 = TE bit is LOW

1 = TE bit is HIGH.

This pin is only sampled during reset of the processor.

CFGEND0I-

Controls the state of EE bit in the CP15 c1 Control Register at reset:

0 = EE bit is LOW

1 = EE bit is HIGH.

This pin is only sampled during reset of the processor.

CFGNMFII-

Configures fast interrupts to be nonmaskable:

0 = clears the NMFI bit in the CP15 c1 Control Register

1 = sets the NMFI bit in the CP15 c1 Control Register.

This pin is only sampled during reset of the processor.

CP15SDISABLEI-Disables CP15.
CPEXIST[13:0]I-

Enables access programming of coprocessors 0-13:

0 = CP0-CP13 cannot be programmed for access

1 = CP0-CP13 can be programmed for access.

This pin is only sampled during reset of the processor. See c1, Coprocessor Access Control Register for more details.

SILICONID[31:0]I-

Defines the reset value of the CP15 Silicon ID Register. See c0, Silicon ID Register for more information.

This pin is only sampled during reset of the processor.

nPMUIRQOb1

Active-LOW PMU interrupt signal:

0 = PMU interrupt active

1 = PMU interrupt not active.

CLKI-Clock input.
CLAMPCOREOUT[1]I-

Activates the clamps to force the core outputs to benign values:

0 = core clamps not active

1 = core clamps active.

CLAMPNEONOUTaI-

Activates the clamps to force the NEON outputs to benign values:

0 = NEON clamps not active

1 = NEON clamps active.

CLAMPDBGOUTaI-

Activates the clamps to force the debug PCLK, ETM CLK, and ETM ATCLK outputs to benign values:

0 = debug and ETM clamps not active

1 = debug and ETM clamps active.

[1] This signal might not be present depending on the IEM support configurable options of the processor.


Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential