13.1.2. VFP coprocessor

The VFP coprocessor implements the VFPv3 architecture. The VFP coprocessor provides a floating-point computation coprocessor that is fully compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, referred to in this document as the IEEE 754 standard. The VFP coprocessor supports all data-processing instructions and data types in the VFPv3 architecture and is described in the ARM Architecture Reference Manual.

Designed for the processor, the VFP coprocessor fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. Conversions between fixed-point and floating-point data formats, and floating-point constant instruction are provided.

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