2.13.1. The state register set

In ARM state, 16 data registers and one or two status registers are accessible at any time. In privileged modes, mode-specific banked registers become available. Figure 2.10 shows which registers are available in each mode.

Thumb and ThumbEE state give access to the same set of registers as ARM state. However, the 16-bit instructions provide only limited access to some of the registers. No such limitations exist for 32-bit Thumb-2 and ThumbEE instructions.

Registers r0 through r13 are general-purpose registers used to hold either data or address values.

Registers r14 and r15 have the following special functions:

Link Register

Register r14 is used as the subroutine Link Register (LR).

Register r14 receives the return address when the processor executes a Branch with Link (BL or BLX) instruction.

You can treat r14 as a general-purpose register at all other times. Similarly, the corresponding banked registers r14_mon, r14_svc, r14_irq, r14_fiq, r14_abt, and r14_und hold the return values when the processor receives interrupts and exceptions, or when it executes the BL or BLX instructions within interrupt or exception routines.

Program Counter

Register r15 holds the PC:

  • in ARM state, this is word-aligned

  • in Thumb state, this is halfword-aligned

  • in ThumbEE state, this is halfword-aligned.

One of the status registers, the Current Program Status Register (CPSR), contains condition code flags, status bits, and current mode bits.

In privileged modes, another register, one of the Saved Program Status Registers (SPSR), is accessible. This contains the condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the current mode. Typically, this is used when returning after handling an exception.

Banked registers have a mode identifier that indicates the mode that they relate to. Table 2.9 shows these mode identifiers.

Table 2.9. Register mode identifiers

Mode

Mode identifier

User

usr

Fast interrupt

fiq

Interrupt

irq

Supervisor

svc

Abort

abt

System

usr

Undefined

und

Monitor

mon


The usr mode identifier is usually omitted from register names. It is only used in descriptions where the User or System mode register is specifically accessed from another operating mode.

FIQ mode has seven banked registers mapped to r8–r14, that is, r8_fiq through r14_fiq. As a result many FIQ handlers do not have to save any registers.

The Monitor, Supervisor, Abort, IRQ, and Undefined modes have alternative mode-specific registers mapped to r13 and r14, that permits a private stack pointer and link register for each mode.

Figure 2.10 shows the ARM state registers.

Figure 2.10. Register organization in ARM state


Figure 2.11 shows an alternative view of the ARM registers.

Figure 2.11. Processor register set showing banked registers


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