2.15.3. Reset

When the reset signals, as described in Chapter 10 Clock, Reset, and Power Control, are driven appropriately a reset occurs, and the processor abandons the executing instruction.

When the reset signals are deasserted, the processor:

  1. Forces the NS bit in SCR to 0 for secure and CPSR M[4:0] to 5'b10011 for secure Supervisor mode.

  2. Sets the A, I, and F bits in the CPSR.

  3. Clears the CPSR J bit. The CPSR T bit is set based on the state of the CFGTE input. Other bits in the CPSR are indeterminate.

  4. Forces the PC to fetch the next instruction from the reset vector address.

  5. Resumes execution in ARM or Thumb state based on the state of the CFGTE input.

After reset, all register values except the PC and CPSR are indeterminate.

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