9.1.1. External interface servicing instruction fetch transactions

The L2 memory system handles all instruction-side cache misses, including those for noncacheable memory. All instruction fetch requests are read-only and are routed to the external read address and data channels. For cacheable memory accesses, a wrapping burst transaction is generated to fetch an entire cache line from external memory. A nonwrapping burst transaction is generated by the L2 memory system for noncacheable, strongly ordered, or device memory instruction fetch accesses. See Table 9.5 for information on AXI instruction transactions.

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