9.1.2. External interface servicing data transactions

The L2 memory system handles all data-side cache misses, including those for noncacheable memory, and those generated by the preload engine. Read data accesses are routed to the read address and data channels, whereas write data accesses are routed to the write address and data channels. Swap and semaphore instruction support is also built into the L2 memory system and external interface that are unique to data-side accesses.

Cacheable accesses generate a wrapping burst transaction on the external interface. Strongly ordered, device, and noncacheable accesses typically result in single transaction requests to external interface. See Table 9.7 for information on data transactions.

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