9.3.1. AXI instruction address transactions

Table 9.5 shows the values of ARADDR[31:0], ARLEN[3:0], ARSIZE[2:0], ARBURST[1:0], and ARLOCK[1:0] for instruction transactions.

Table 9.5. AXI address channel for instruction transactions

TransferBus widthARADDR [31:0][1]ARLEN[3:0]ARSIZE[2:0]ARBURST[1:0]ARLOCK [1:0]
MMU translation table translation table walk[2]64[31:6]bbbb00 032-bitIncrNormal
128[31:6]bbbb00 032-bitIncrNormal
Noncacheable64[31:6]bbb0000-764-bitIncrNormal
128[31:6]bb00000-3128-bitIncrNormal
Cacheable linefill64[31:6]bbb000764-bitWrapNormal
128[31:6]bb00003128-bitWrapNormal

[1] ARADDR[31:0] is a 32-bit signal with bits [5:3] set to any value and bits [2:0] set to 0, unless otherwise indicated. This determines the ARLEN[3:0] value depending on the transfer type and bus width. For example, a noncacheable instruction fetch with ARADDR[5:0] = b101000 for a 64-bit bus width, results in an ARLEN[3:0] = b0010. In this example, doublewords 5, 6, and 7 of the cache line are transferred.

[2] This is for noncacheable or strongly ordered table walk only. For cacheable table walk, the bus transaction is a cacheable linefill.


Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential