9.4.4. AXI data address transactions

Table 9.7 shows the values of AxADDR[31:0], AxLEN[3:0], AxSIZE[2:0], AxBURST[1:0], and AxLOCK[1:0] for data transactions excluding load/store multiples.

In this table:

NA

Naturally Aligned

BW

Bus Width

BC

Boundary Cross

NoT

Number of Transactions

TS

Transaction sequence number if multiple transactions are required

SAO

Starting Address Offset

AxA

AxADDR, either ARADDR or AWADDR

AxLN

AxLEN, either ARLEN or AWLEN

AxS

AxSIZE, either ARSIZE or AWSIZE

AxB

AxBURST, either ARBURST or AWBURST

AxLK

AxLOCK, either ARLOCK or AWLOCK

Table 9.7. AXI address channel for data transactions - excluding load/store multiples

TransferNABWBC[1]NoTTSSAO [3:0]AxA [31:0]AxLN [3:0]AxS [2:0]AxB [1:0]AxLK [1:0]
MMU translation table walk[2]Yes64N/A1--[31:2]00032-bitIncrNormal
128N/A1--[31:2]00032-bitIncrNormal
Noncacheable, or strongly ordered, or device load byteYes64N/A1--[31:0]08-bitIncrNormal
128N/A1--[31:0]08-bitIncrNormal
Noncacheable, or strongly ordered, or device load halfwordYes64N/A1--[31:1]0016-bitIncrNormal
128N/A1--[31:1]0016-bitIncrNormal
Noncacheable load halfwordNo64QW21st-[31:1]0016-bitIncrNormal
QW22nd-[31:4]0000016-bitIncrNormal
DW1--[31:1]0116-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
HW1--[31:2]00032-bitIncrNormal
128QW21st-[31:1]0016-bitIncrNormal
   2nd-[31:4]0000016-bitIncrNormal
 DW1--[31:4]00000128-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
HW1--[31:2]00032-bitIncrNormal
Noncacheable, or strongly ordered, or device load wordYes64N/A1--[31:2]00032-bitIncrNormal
128N/A1--[31:2]00032-bitIncrNormal
Noncacheable load wordNo64QW21st-[31:2]00032-bitIncrNormal
    2nd-[31:4]0000032-bitIncrNormal
  DW1--[31:2]00132-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
128QW21st-[31:2]00032-bitIncrNormal
   2nd-[31:4]0000032-bitIncrNormal
DW1--[31:4]00000128-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
Noncacheable, or strongly ordered, or device load doublewordYes64N/A1--[31:3]000064-bitIncrNormal
128N/A1--[31:3]000064-bitIncrNormal
Noncacheable, or strongly ordered, or device load doublewordNo64QW21st-[31:2]00032-bitIncrNormal
    2nd-[31:4]0000032-bitIncrNormal
  DW21st-[31:2]00032-bitIncrNormal
    2nd-[31:3]000032-bitIncrNormal
128QW21st-[31:2]00032-bitIncrNormal
   2nd-[31:4]0000032-bitIncrNormal
DW21st-[31:2]00032-bitIncrNormal
  2nd-[31:3]000032-bitIncrNormal
Noncacheable, or strongly ordered, or device store byteYes64N/A1--[31:0]08-bitIncrNormal
128N/A1--[31:0]08-bitIncrNormal
Noncacheable, or strongly ordered, or device store halfwordYes64N/A1--[31:1]0016-bitIncrNormal
128N/A1--[31:1]0016-bitIncrNormal
Noncacheable store halfwordNo64QW21st-[31:0]08-bitIncrNormal
  2nd-[31:4]000008-bitIncrNormal
DW1--[31:0]18-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
HW1--[31:3]000064-bitIncrNormal
128QW21st-[31:0]08-bitIncrNormal
   2nd-[31:4]000008-bitIncrNormal
 DW1--[31:4]00000128-bitIncrNormal
 W1--[31:3]000064-bitIncrNormal
 HW1--[31:3]000064-bitIncrNormal
Noncacheable, or strongly ordered, or device store wordYes64N/A1--[31:2]00032-bitIncrNormal
128N/A1--[31:2]00032-bitIncrNormal
Noncacheable store wordNo64QW21st0xD[31:3]000032-bitIncrNormal
2nd-[31:4]000008-bitIncrNormal
1st0xE[31:4]1110016-bitIncrNormal
2nd-[31:4]0000016-bitIncrNormal
1st0xF[31:4]111108-bitIncrNormal
2nd-[31:4]0000064-bitIncrNormal
DW1-0x5[31:3]000164-bitIncrNormal
0x6[31:3]110116-bitIncrNormal
0x7[31:3]000164-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
128QW21st0xD[31:3]000064-bitIncrNormal
2nd-[31:4]000008-bitIncrNormal
1st0xE[31:4]1110016-bitIncrNormal
2nd-[31:4]0000016-bitIncrNormal
1st0xF[31:4]111108-bitIncrNormal
2nd-[31:4]0000064-bitIncrNormal
DW1-0x5[31:4]00000128-bitIncrNormal
0x6[31:4]00000128-bitIncrNormal
0x7[31:4]00000128-bitIncrNormal
W1--[31:3]000064-bitIncrNormal
Noncacheable, or strongly ordered, or device store doublewordYes64N/A1--[31:3]000064-bitIncrNormal
128N/A1--[31:3]000064-bitIncrNormal
Noncacheable store doublewordNo64QW21st-[31:2]00032-bitIncrNormal
 2nd-[31:4]0000032-bitIncrNormal
DW1[3]--[31:2]00132-bitIncrNormal
2[4]1st-[31:2]00032-bitIncrNormal
128QW21st-[31:2]00032-bitIncrNormal
 2nd-[31:4]0000032-bitIncrNormal
DW1--[31:4]00000128-bitIncrNormal
Strongly ordered, or device store doublewordNo64QW21st-[31:2]00032-bitIncrNormal
   2nd-[31:4]0000032-bitIncrNormal
 DW21st-[31:2]00032-bitIncrNormal
   2nd-[31:3]000032-bitIncrNormal
128QW21st-[31:2]00032-bitIncrNormal
  2nd-[31:4]0000032-bitIncrNormal
DW21st-[31:2]00032-bitIncrNormal
     2nd-[31:3]000032-bitIncrNormal
Cacheable linefillYes64N/A8--[31:3]000764-bitWrapNormal
128N/A4--[31:4]00003128-bitWrapNormal
Eviction/castoutYes64N/A8--[31:3]000764-bitIncrNormal
128N/A4--[31:4]00003128-bitIncrNormal
Swap byte (load/store)Yes64N/A1--[31:0]08-bitIncrLocked
128N/A1--[31:0]08-bitIncrLocked
Swap word (load/store)Yes64N/A1--[31:2]00032-bitIncrLocked
128N/A1--[31:2]00032-bitIncrLocked
Exclusive byte (load/store)Yes64N/A1--[31:0]08-bitIncrExclusive
128N/A1--[31:0]08-bitIncrExclusive
Exclusive half word (load/store)Yes64N/A1--[31:1]0016-bitIncrExclusive
128N/A1--[31:1]0016-bitIncrExclusive
Exclusive word (load/store)Yes64N/A1--[31:2]00032-bitIncrExclusive
128N/A1--[31:2]00032-bitIncrExclusive
Exclusive doubleword (load/store)Yes64N/A1--[31:3]000064-bitIncrExclusive
128N/A1--[31:3]000064-bitIncrExclusive

[1] In the Boundary cross column, HW = 16 bits, W = 32 bits, DW = 64 bits, and QW = 128 bits.

[2] This is for noncacheable or strongly ordered table walk only. For cacheable table walk, the bus transaction is a cacheable linefill.

[3] This is for write combining enabled.

[4] This is for write combining disabled.


Table 9.8 shows the values of ARADDR[31:0], ARLEN[2:0], ARSIZE[2:0], ARBURST[1:0], ARLOCK[1:0], and ARPROT[2:0] for data transactions for load/store multiples.

In this table:

ENR

Even Number Registers

FA

First Access

LA

Last Access

Table 9.8. AXI address channel for data transactions for load/store multiples

TransferAlignmentENRFALAARADDR [31:0]ARLEN [2:0]ARSIZE [2:0]ARBURST [1:0]ARLOCK [1:0]
Noncacheable, or strongly ordered, or device LDMsEven wordYes10[31:3]000064-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal
11[31:3]000064-bitIncrNormal
No10[31:3]000064-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal
11[31:3]000032-bitIncrNormal
 Odd wordYes10[31:2]00032-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000032-bitIncrNormal
No10[31:2]00032-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal
Noncacheable, or strongly ordered, or device STMsEven wordYes10[31:3]000064-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal
11[31:3]000064-bitIncrNormal
No10[31:3]000064-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal
11[31:3]000032-bitIncrNormal
 Odd wordYes10[31:3]100032-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000032-bitIncrNormal
No10[31:3]100032-bitIncrNormal
00[31:3]000064-bitIncrNormal
01[31:3]000064-bitIncrNormal

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