10.1.1. AXI clocking using ACLKEN

The processor contains a single synchronous AXI interface. The AXI interface is clocked using a gated CLK that is gated using ACLKEN. The AXI interface can operate at any integer multiple slower than the processor clock, CLK. In previous ARM family of processors, sampling ACLKEN on the rising edge of CLK indicated that the rising edge of the AXI bus clock, ACLK, had occurred. However, for the processor, the cycle timing of ACLKEN has changed.

Figure 10.2 shows the timing behavior of ACLKEN.

Figure 10.2. CLK-to-ACLK ratio of 4:1


Note

Figure 10.2 shows the timing relationship between the AXI bus clock, ACLK, and ACLKEN, where ACLKEN asserts two CLK cycles prior to the rising edge of ACLK. It is critical that the relationship between ACLK and ACLKEN is maintained.

Figure 10.3 shows a change to a 1:1 clock ratio. In this figure, ACLKEN remains asserted, changing the CLK:ACLK frequency ratio from 4:1 to 1:1.

Figure 10.3. Changing the CLK-to-ACLK ratio from 4:1 to 1:1


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