12.3.4. Memory-mapped registers

Table 12.3 shows the complete list of memory-mapped registers accessible using the APB interface.

Note

You must ensure that the base address of this 4KB register region is aligned to a 4KB boundary in physical memory.

Table 12.3. Debug memory-mapped registers

Offset

Register

number

AccessMnemonic

Power

domain

Description
0x000c0RDIDRDebugCP14 c0, Debug ID Register
0x004-0x014c1-c5R--RAZ
0x18c6RWWFARCoreWatchpoint Fault Address Register
0x01Cc7RWVCRCoreVector Catch Register
0x020c8R--RAZ
0x024c9RWECRDebugEvent Catch Register
0x028c10RWDSCCRCoreDebug State Cache Control Register
0x02Cc11R--RAZ
0x030-0x07Cc12-c31R--RAZ
0x080c32RWDTRRXCoreData Transfer Register
0x084c33WITRCoreInstruction Transfer Register
0x088c34RWDSCRCoreCP14 c1, Debug Status and Control Register
0x08Cc35RWDTRTXCoreData Transfer Register
0x090c36WDRCRDebugDebug Run Control Register
0x094-0x0FCc37-c63R--RAZ
0x100-0x114c64-c69RWBVRCoreBreakpoint Value Registers
0x118-0x13Cc70-c79R--RAZ
0x140-0x154c80-c85RWBCRCoreBreakpoint Control Registers
0x158-0x17Cc86-c95R--RAZ
0x180-0x184c96-c97RWWVRCoreWatchpoint Value Registers
0x188-0x1BCc97-c111R--RAZ
0x1C0-0x1C4c112-c113RWWCRCoreWatchpoint Control Registers
0x1C8-0x1FCc114-c127R--RAZ
0x200-0x2FCc128-c191R--RAZ
0x300c192WOSLARDebugOperating System Lock Access Register
0x304c193ROSLSRDebugOperating System Lock Status Register
0x308c194RWOSSRR-Operating System Save and Restore Register
0x30Cc195R--RAZ
0x310c196RWPRCRDebugDevice Power Down and Reset Control Register
0x314c197RPRSRDebugDevice Power Down and Reset Status Register
0x318-0x7FCc198-c511R--RAZ
0x800-0x8FCc512-575R--RAZ
0x900-0xCFCc576-c831R--RAZ
0xD00-0xFFCc832-c1023---Management registers

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