12.3.7. Effects of resets on debug registers

The processor has three reset signals that affect the debug registers in the following ways:


The system asserts this signal when powering up the core domain. It sets all of the core power domain logic to the reset value, including all debug registers in the core power domain.


The system asserts this signal for a warm or soft reset. It sets all the processor logic except debug or ETM, to the reset value. Therefore, the state of a debug or trace session is not affected by this reset signal.


The system asserts this signal to set all of the debug and ETM logic to the reset value.

Table 12.4 shows the processor reset effect on debug and ETM logic.

Table 12.4. Processor reset effect on debug and ETM logic

SignalDebug power domainCore power domain
 Debug and ETM logicDebug and ETM logicNon-debug and non-ETM logic
nPORESETNot resetResetReset
ARESETnNot resetNot resetReset
PRESETnResetResetNot reset

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