12.8.1. Entering debug state

When a debug event occurs while the processor is in Halting debug-mode, it switches to a special state called debug state so the debugger can take control. You can configure Halting debug-mode by setting DSCR[14] to 1.

If a halting debug event occurs, the processor enters debug state even when Halting debug-mode is not configured.

While the processor is in debug state, the PC does not increment on instruction execution. If the PC is read at any point after the processor has entered debug state, but before an explicit PC write, it returns a value as described in Table 12.54, depending on the previous state and the type of debug event.

Table 12.54 shows the read PC value after debug state entry for different debug events. The ARM and the Thumb and ThumbEE columns in this table represent the processor state in which the exception occurred.

Table 12.54. Read PC value after debug state entry

Debug eventARMThumb and ThumbEEReturn address (RA) meaning
BreakpointRA+8RA+4Breakpointed instruction address
WatchpointRA+8RA+4Address of the instruction that triggered the watchpoint debug event
BKPT instructionRA+8RA+4BKPT instruction address
Vector catchRA+8RA+4Vector address
External debug request signal activationRA+8RA+4Address of the instruction that the external debug request signal activation canceled
Debug state entry request commandRA+8RA+4Address of the instruction that the debug state entry request command canceled
OS unlock catch eventRA+8RA+4Address of the instruction that the OS unlock catch event canceled
CTI debug request signal activationRA+8RA+4Address of the instruction that the CTI debug request signal activation canceled

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