12.8.4. Writing to the CPSR in debug state
The only instruction that can update the CPSR while in debug
state is the MSR instruction. All other ARMv7 instructions
that write to the CPSR are Unpredictable, that is, the BX, BXJ, SETEND, CPS, RFE, LDM(3),
and data processing instructions with Rd == r15 and S == 1.
The behavior of the CPSR forms of the MSR and MRS instructions
in debug state is different to their behavior in normal state:
When not in debug state, an MSR instruction
that modifies the execution state bits in the CPSR is Unpredictable.
However, in debug state an MSR instruction can update
the execution state bits in the CPSR. A direct modification of the
execution state bits in the CPSR by an MSR instruction
must be followed by an instruction memory barrier sequence.
When not in debug state, an MRS instruction
reads the CPSR execution state bits as zeros. However, in debug
state an MRS instruction returns the actual values
of the execution state.
The debugger must execute an instruction memory barrier sequence
after it writes to the CPSR execution state bits using an MSR instruction.
If the debugger reads the CPSR using an MRS instruction
after a write to any of these bits, but before an instruction memory
barrier sequence, the value that MRS returns is Unpredictable.
Similarly, if the debugger forces the processor to leave debug state
after an MSR writes to the execution state bits, but
before any instruction memory barrier sequence, the behavior of
the processor in Unpredictable.
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