12.9.1. Cache pollution in debug state

If bit [0] of the Debug State Cache Control Register (DSCCR) is set to 0 while the processor is in debug state, then neither the L1 data cache or L2 cache performs any eviction or linefill. However, evictions still occur in any of the following cases:


No special feature is required to prevent L1 instruction cache pollution because I-side fetches cannot occur while in debug state.

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