12.10.1. Miscellaneous debug signals

This section describes some of the miscellaneous debug input and output signals.

EDBGRQ

This signal generates a halting debug event, that is, it requests the processor to enter debug state. When this occurs, the DSCR[5:2] method of debug entry bits are set to b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so leads to Unpredictable behavior of the processor.

DBGACK

The processor asserts DBGACK to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQ signal. The processor also drives the DBGACK signal HIGH when the debugger sets the DSCR[10] DbgAck bit to 1.

COMMRX and COMMTX

The COMMRX and COMMTX output signals enable interrupt-driven communications over the DTR. By connecting these signals to an interrupt controller, software using the debug communications channel can be interrupted whenever there is new data on the channel or when the channel is clear for transmission.

COMMRX is asserted when the CP14 DTR has data for the processor to read, and it is deasserted when the processor reads the data. Its value is equal to DSCR[30] DTRRXfull flag.

COMMTX is asserted when the CP14 is ready for write data, and it is deasserted when the processor writes the data. Its value equals the inverse of DSCR[29] DTRTXfull flag.

DBGNOPWRDWN

The processor asserts DBGNOPWRDWN when bit [0] of the Device Power Down and Reset Control Register is 1. The processor power controller works in emulate mode when this signal is HIGH.

DBGPWRDWNREQ

You must set the DBGPWRDWNREQ signal HIGH before removing power from the core domain. Bit [0] of the Device Power Down and Reset Status Register reflects the value of this DBGPWRDWNREQ signal.

Note

DBGPWRDWNREQ must be tied LOW if the particular implementation does not support separate core and debug power domains.

DBGPWRDWNACK

This signal indicates to the system that it is safe to bring the core voltage down.

Figure 12.29 shows the relationship of the DBGPWRDWNREQ and DBGPWRDWNACK signals with the core domain power-down and power-up sequences.

Figure 12.29. Timing of core power-down and power-up sequences


DBGOSLOCKINIT

When the DBGOSLOCKINIT signal is asserted on PRESETn reset, the OS lock is set. Otherwise, the OS lock is clear on PRESETn reset. ARM recommends that this signal is tied LOW.

DBGROMADDR

The DBGROMADDR signal specifies bits [31:12] of the debug ROM physical address. This is a configuration input and must be tied off or changed while the processor is in reset. In a system with multiple debug ROMs, this address must be tied off to point to the top-level ROM address.

DBGROMADDRV is the valid signal for DBGROMADDR. If the address cannot be determined, DBGROMADDR must be tied off to zero and DBGROMADDRV must be tied LOW.

DBGSELFADDR

The DBGSELFADDR signal specifies bits [31:12] of the offset of the debug ROM physical address to the physical address where the APB interface is mapped to the base of the 4KB debug register map. This is a configuration input and must be tied off or changed while the processor is in reset.

DBGSELFADDRV is the valid signal for DBGSELFADDR. If the offset cannot be determined, DBGSELFADDR must be tied off to zero and DBGSELFADDRV must be tied LOW.

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential