14.1.1. ETM features

The ETM has the following main features:

Core interface module

The core interface module monitors the behavior of the processor.

Trace generation

The ETM generates a real-time trace that can be configured to include:

  • instruction tracing containing:

    • the addresses of executed instructions

    • passed or failed condition codes of the instructions

    • information about exceptions

    • context IDs.

  • data address tracing containing the addresses of data transfers as viewed by the ARM architecture.


The Cortex-A8 ETM does not support tracing of data values.

Filtering and triggering resources

You can filter the ETM trace such as configuring it to trace only instructions or data transfers in certain address ranges. You can also configure the ETM to filter based on the values of data transfers even though these cannot be traced. More complicated logic analyzer style filtering options are also available.

The ETM can also generate a trigger that is a signal to the trace capture device to stop capturing trace.


The trace generated by ETM is in a highly compressed form. The main FIFO enables bursts caused by the trace compression to be flattened out. When the FIFO becomes full, the FIFO signals an overflow. The trace generation logic does not generate any new trace until the FIFO has emptied. This causes a gap in the trace when viewed in the debugger.

You can also configure the ETM to suppress data address tracing when the FIFO is close to being full. This can prevent overflows from occurring.

AMBA 3 ATB interface

The ETM outputs trace using the AMBA 3 Advanced Trace Bus (ATB) interface. See the CoreSight Architecture Specification for more information on AMBA 3 ATB.

You can output trace asynchronously to the core clock.

AMBA 3 APB interface

The AMBA 3 Advanced Peripheral Bus (APB) interface enables access to the ETM, CTI, and the debug registers. The APB interface is compatible with the CoreSight architecture which is the ARM architecture for multi-processor trace and debug. See the CoreSight Architecture Specification for more information.

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