16.2.1. Example of how to read ARM instruction tables

This section provides examples of how to read ARM instruction tables described in the chapter. See the ARM Architecture Reference Manual for assembly syntax of instructions.

Example 16.1 shows how to read an ADDEQ data-processing instruction from Table 16.1.

Example 16.1. Data-processing instruction

ADDEQ R0, R1, R2 LSL#10

This is a conditional general data-processing instruction of type shift by immediate. Source1, in this case R1, is required in E2 and Source2, in this case R2, is required in E1. Because the instruction is conditional, the destination register R0 is also required as a source register and must be available in E2. The result, stored in R0 for this case, is available in E2 for the next subsequent instruction that requires this register as a source operand. Assuming no data hazards, the instruction takes a minimum of one cycle to execute as indicated by the value in the Cycles column.


Example 16.2 shows how to read an SMLAL multiply instruction from Table 16.4.

Example 16.2. Multiply instruction

SMLAL R0, R1, R2, R3

This is a multiply accumulate instruction. Source1, in this case R2, and Source2, in this case R3, are both required in E1. Because this is an accumulate multiply instruction, the result registers, R0 and R1, in this case are both required as source registers in E1. The result, stored in R0 and R1, for this case is available in E5 for the next subsequent instruction that requires one or both of these registers as a source operand. Assuming no data hazards, the instruction takes a minimum of three cycles to execute as indicated by the value in the Cycles column.


Example 16.3 shows how to read an LDR PC load instruction from Table 16.9.

Example 16.3. Load instruction

LDR PC, [R13,#4]

This is a load instruction of type immediate offset. However, it is also a branch instruction because the PC is the destination. Source1, in this case R13, is required in E1. Because writeback is enabled on this load instruction, Source1, in this case R13, is also required as a result destination register for writing back the new address. This result is available in E2 for the next subsequent instruction that requires this register as a source operand. Assuming no data hazards, the instruction takes a minimum of one cycle to execute as indicated by the value in the Cycles column. To complete the timing calculation for this instruction, we use information for the branch instructions as shown in Table 16.11. In this table, we can see that the instruction is unconditional, therefore no flags are required as a source in E3 for branch resolution. The Cycles column of Table 16.11 indicates to add one cycle to the total execution time for all load instructions that are branches. Assuming no data hazards, the instruction takes a minimum of two cycles instead of one cycle.


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